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Home > Products > Integrated Circuits (ICs) > Logic > Multivibrators

Texas Instruments SN74LS123N-P2

Name: SN74LS123N-P2
Brand: Texas Instruments
SKU: SN74LS123N-P2
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74LS123N-P2

Manufacturer:: Texas Instruments

Category:: Multivibrators

Package:: 16-DIP (0.300", 7.62mm)

Datasheet:: SN74LS123N-P2.pdf

Description:: PROTOTYPE

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Product details

Overview

SN74LS123N-P2 from Texas Instruments is a dual retriggerable monostable multivibrator IC used for precise pulse generation, timing control, and event debouncing in TTL-compatible digital systems. It features two independent monostable circuits, 16-pin PDIP package, 0°C to 70°C operating temperature, typical output propagation delay of 45 ns at V_CC = 5 V, and supports both rising- and falling-edge triggering on each input.

For engineers reviewing the SN74LS123N-P2 datasheet, SN74LS123N-P2 pinout, SN74LS123N-P2 application, or SN74LS123N-P2 equivalent, this page delivers verified functional identity, confirmed timing parameters, validated package mapping, real-world use cases, and technically documented alternative options for legacy TTL timing design.

Technical Context

The SN74LS123N-P2 implements two identical, independently configurable monostable multivibrators with retriggerable behavior-allowing new trigger events to extend or restart the output pulse before timeout. Each section uses external RC networks (R_A/C_A, R_B/C_B) to set pulse width, supporting adjustable delays from ~30 ns to >30 s.

It operates strictly in TTL logic families, with input thresholds compatible with standard 74LS levels, guaranteed high-impedance outputs during power-up, and no internal pull-ups-requiring external termination for unused inputs. The device does not include Schmitt-trigger inputs or programmable reset, distinguishing it from later-generation monostables.

Key Specifications

Parameter	Value and Actual Design Meaning
Function	Dual retriggerable monostable multivibrator for TTL-level pulse shaping and timing
Supply Voltage	4.75 V to 5.25 V - requires regulated 5 V rail; operation outside this range invalidates timing specs
Pulse Width Range	30 ns to >30 s per section - set by external R/C components; minimum width limited by internal propagation delay
Propagation Delay	45 ns typical (A→Q), 35 ns typical (B→Q) at V_CC = 5 V, T_A = 25°C - defines minimum resolvable timing interval
Operating Temperature	0°C to 70°C - commercial-grade rating; not qualified for extended or military temperature ranges
Package	16-pin plastic DIP (PDIP-N) - through-hole mounting; 0.3-inch body width; RoHS-compliant NiPdAu lead finish

Pinout & Package

SN74LS123N-P2 is housed in a 16-pin plastic dual in-line package (PDIP-N) with 0.3-inch width, 0.1-inch lead pitch, and standard DIP footprint compatible with through-hole PCB assembly and socketing.

Pin/Terminal	Circuit Role	Design Meaning
1A, 1B	Section 1 trigger inputs	1A: negative-edge trigger; 1B: positive-edge trigger - both must be used together for edge selection
1R̅	Section 1 reset	Active-low asynchronous reset - forces Q1 low regardless of trigger state or timing
1Q, 1Q̅	Section 1 complementary outputs	Q1: active-high monostable output; Q1̅: inverted copy - both driven simultaneously
2A, 2B	Section 2 trigger inputs	2A: negative-edge trigger; 2B: positive-edge trigger - independent of Section 1
2R̅	Section 2 reset	Active-low asynchronous reset - isolated from Section 1; no cross-section interaction
2Q, 2Q̅	Section 2 complementary outputs	Q2: active-high monostable output; Q2̅: inverted copy - fully independent timing path
V_CC, GND	Power supply terminals	V_CC = Pin 16, GND = Pin 8 - decoupling capacitor (0.1 µF ceramic) required at each supply pin

Key Features

Feature	Design Value
Retriggerable operation	Enables continuous pulse extension during ongoing events - essential for switch debouncing and serial data pulse stretching
Dual independent sections	Eliminates need for two discrete monostables; reduces board space and interconnect complexity in multi-timing applications
Edge-selectable triggering	Supports either rising or falling edge via A/B input pairing - avoids external inverters for polarity adaptation
Asynchronous reset per section	Allows deterministic output termination without waiting for timeout - critical for fault recovery and system synchronization
TTL-compatible I/O	Guaranteed interface with 74LS, 74S, and 74F families - no level-shifting required in legacy digital designs

Applications

Keyboard Debounce Circuit	Serial Data Pulse Stretching
Use Scenario: Mechanical keyboard matrix scanning where contact bounce causes multiple false keypress detections. IC Role / Device Role / Timing Role: SN74LS123N-P2 Section 1 acts as a hardware debouncer, generating a clean 20-ms stable output pulse per keypress. Use Value: Eliminates software polling overhead and ensures reliable key registration at microcontroller GPIO inputs.	Use Scenario: Legacy UART or RS-232 receiver circuit requiring minimum pulse width compliance for start-bit detection. IC Role / Device Role / Timing Role: SN74LS123N-P2 Section 2 extends narrow incoming data pulses to ≥1 µs duration to meet UART sampling window requirements. Use Value: Prevents framing errors caused by undersized pulses from long cable runs or marginal drivers.
Timing Control in Test Equipment	Glitch Suppression in Digital Logic
Use Scenario: Benchtop logic analyzer trigger sequencer needing precise, user-adjustable gate windows for signal capture. IC Role / Device Role / Timing Role: SN74LS123N-P2 provides two synchronized but independently adjustable timing windows using front-panel potentiometers on R/C networks. Use Value: Enables repeatable, analog-tunable timing without firmware updates or FPGA reconfiguration.	Use Scenario: Synchronizing asynchronous control signals (e.g., reset, enable) between clock domains in mixed-signal instrumentation. IC Role / Device Role / Timing Role: SN74LS123N-P2 filters sub-50 ns noise spikes on control lines using fixed 100 ns pulse-width configuration. Use Value: Prevents metastability-induced system lockup while preserving functional signal integrity.

Keyboard Debounce Circuit

Serial Data Pulse Stretching

Use Scenario: Mechanical keyboard matrix scanning where contact bounce causes multiple false keypress detections.

IC Role / Device Role / Timing Role: SN74LS123N-P2 Section 1 acts as a hardware debouncer, generating a clean 20-ms stable output pulse per keypress.

Use Value: Eliminates software polling overhead and ensures reliable key registration at microcontroller GPIO inputs.

Use Scenario: Legacy UART or RS-232 receiver circuit requiring minimum pulse width compliance for start-bit detection.

IC Role / Device Role / Timing Role: SN74LS123N-P2 Section 2 extends narrow incoming data pulses to ≥1 µs duration to meet UART sampling window requirements.

Use Value: Prevents framing errors caused by undersized pulses from long cable runs or marginal drivers.

Timing Control in Test Equipment

Glitch Suppression in Digital Logic

Use Scenario: Benchtop logic analyzer trigger sequencer needing precise, user-adjustable gate windows for signal capture.

IC Role / Device Role / Timing Role: SN74LS123N-P2 provides two synchronized but independently adjustable timing windows using front-panel potentiometers on R/C networks.

Use Value: Enables repeatable, analog-tunable timing without firmware updates or FPGA reconfiguration.

Use Scenario: Synchronizing asynchronous control signals (e.g., reset, enable) between clock domains in mixed-signal instrumentation.

IC Role / Device Role / Timing Role: SN74LS123N-P2 filters sub-50 ns noise spikes on control lines using fixed 100 ns pulse-width configuration.

Use Value: Prevents metastability-induced system lockup while preserving functional signal integrity.

Equivalent & Alternatives

The following parts are listed as comparable options for similar monostable multivibrator applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LS221N	Non-retriggerable dual monostable; 20-pin PDIP; includes internal pull-downs on inputs	Cannot extend pulses mid-cycle - unsuitable for dynamic debounce or variable-duration timing	Select only when fixed-duration, non-overlapping pulses are required and pin count allows 20-pin layout
SN74LS423N	Retriggerable dual monostable with built-in Schmitt-trigger inputs; 16-pin PDIP; higher max pulse width (100 s)	Accepts slow/noisy inputs directly; wider timing range - but consumes more quiescent current (24 mA vs. 18 mA)	Prefer for noisy environments or ultra-long timing; verify power budget and input slew rate compatibility

Compared with SN74LS123N-P2, SN74LS221N offers deterministic single-shot behavior ideal for fixed-interval gating, while SN74LS423N adds noise immunity and extended timing range at the cost of higher static power - all three share 16-pin PDIP compatibility but differ fundamentally in retriggering capability and input conditioning.

Availability

SN74LS123N-P2 is available at Aetrix Electronics and suitable for industrial control panels, legacy test equipment refurbishment, and educational electronics labs requiring stable component supply and long-term obsolescence management.

Supply support for SN74LS123N-P2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog and embedded processing technologies with broad industrial, automotive, and consumer product portfolios.

The SN74LS123N-P2 belongs to TI's legacy 74LS logic family, designed specifically for TTL-compatible digital timing, pulse shaping, and event synchronization in cost-sensitive, through-hole-based systems of the 1970s–1990s.

FAQ

What is the maximum pulse width achievable with SN74LS123N-P2?

The SN74LS123N-P2 supports pulse widths up to approximately 30 seconds per section when using standard external RC values within recommended stability limits. This upper bound is constrained by capacitor leakage, resistor tolerance, and temperature drift-not by internal circuitry. For durations beyond 10 s, film or polystyrene capacitors and precision metal-film resistors are advised to maintain accuracy. The SN74LS123N-P2 datasheet specifies no hard upper limit, but practical reliability degrades above 30 s.

Can SN74LS123N-P2 operate with a 3.3 V supply?

No, SN74LS123N-P2 is not rated for 3.3 V operation. Its absolute maximum supply voltage is 5.5 V, and minimum functional voltage is 4.75 V per the 74LS family specification. At 3.3 V, the internal TTL input thresholds are unmet, resulting in undefined logic states, failed triggering, and unreliable output transitions. Use SN74LVC123A or similar 3.3 V–compatible monostables instead.

Does SN74LS123N-P2 require external pull-up or pull-down resistors on its inputs?

Yes - SN74LS123N-P2 has no internal pull-up or pull-down resistors on any input (1A, 1B, 1R̅, 2A, 2B, 2R̅). Unused inputs must be externally terminated to V_CC or GND to prevent floating nodes, which cause excessive current draw, erratic triggering, and potential damage. For example, tie 1R̅ to V_CC if reset is not used; tie unused trigger inputs to GND for inactive-low or V_CC for inactive-high configuration.

How does retriggering work on SN74LS123N-P2 compared to non-retriggerable monostables?

When a new trigger arrives during an active output pulse, SN74LS123N-P2 restarts the timing cycle from zero - extending the total output duration. In contrast, non-retriggerable devices like SN74LS221N ignore subsequent triggers until the current pulse completes. This makes SN74LS123N-P2 ideal for applications such as mechanical switch debouncing, where repeated bounces must prolong the clean output window, rather than generate discrete pulses.

Is SN74LS123N-P2 pin-compatible with SN74LS122N?

No, SN74LS123N-P2 is not pin-compatible with SN74LS122N. The SN74LS122N is a 14-pin device with different pin assignments, single-section architecture, and distinct trigger logic (non-retriggerable, different input configuration). Attempting direct replacement will result in incorrect connections, missing functions, and potential damage. Always verify pinout diagrams and functional block diagrams before substitution - SN74LS123N-P2 requires a 16-pin footprint and dual-section wiring.

SN74LS123N-P2 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74LS

Package/Case:: 16-DIP (0.300", 7.62mm)

Packaging:: Bulk

Product Status:: Active

Logic Type:: Monostable

Independent Circuits:: 2

Schmitt Trigger Input:: No

Propagation Delay:: 34 ns

Current - Output High, Low:: 8mA, 400µA

Voltage - Supply:: 4.75 V ~ 5.25 V

Operating Temperature:: 0°C ~ 70°C

Grade:: -

Qualification:: -

Mounting Type:: Through Hole

Supplier Device Package:: 16-PDIP

SN74LS123N-P2 FAQ

1.How can I place an order for SN74LS123N-P2 through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74LS123N-P2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74LS123N-P2 reliable?

The price and inventory of SN74LS123N-P2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS123N-P2 is usually 5 days.

3.What payment methods are accepted for SN74LS123N-P2?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS123N-P2 transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74LS123N-P2?

SN74LS123N-P2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74LS123N-P2 order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74LS123N-P2?

For technical support, including SN74LS123N-P2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS123N-P2 requirements.

6.How does Aetrix verify that SN74LS123N-P2 is sourced from the original manufacturer or authorized distributors?

All SN74LS123N-P2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS123N-P2 meets industry standards.

7.What is the process for return or replacement of SN74LS123N-P2?

All SN74LS123N-P2 units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS123N-P2, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74LS123N-P2 part is unused and in its original packaging.

Return procedure for SN74LS123N-P2:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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