Texas Instruments SN74LS123NSRG4
- Part No.:
- SN74LS123NSRG4
- Manufacturer:
- Texas Instruments
- Category:
- Multivibrators
- Package:
- 16-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
SN74LS123NSRG4.pdf
- Description:
- IC MULTIVIBRATOR 28NS 16SO
- Quantity:
- Payment:

- Shipping:

Inventory:2,668
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Product details
Overview
SN74LS123NSRG4 from Texas Instruments is a dual retriggerable monostable multivibrator IC in 16-pin SOP (NS) package, operating over 0°C to 70°C, with typical output pulse width of 15 ns at VCC = 5 V and CL = 15 pF, used for precise timing control in digital logic interfacing and pulse shaping circuits.
For engineers reviewing the SN74LS123NSRG4 datasheet, SN74LS123NSRG4 pinout, SN74LS123NSRG4 application, or SN74LS123NSRG4 equivalent, this page delivers verified functional identity, confirmed SOP-16 pin mapping, temperature-rated performance data, and validated alternative options for legacy TTL timing design.
Technical Context
The SN74LS123NSRG4 implements two independent retriggerable monostable multivibrators per package, each with separate A and B trigger inputs, reset (R̅), Q and Q̅ outputs, and external RC timing networks. Each section supports both positive-edge (A input) and negative-edge (B input) triggering.
Timing is set by external resistor (R) and capacitor (C) values, with nominal pulse width tW = 0.33 × R × C. Propagation delay from trigger to Q output is typically 15 ns at VCC = 5 V, and output drive capability meets LS-TTL specifications: IOH = –0.4 mA, IOL = 8 mA.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | Dual retriggerable monostable multivibrator - enables pulse extension on repeated triggers without resetting output state |
| Supply Voltage | 4.75 V to 5.25 V - compatible with standard 5 V TTL logic rails and noise margins |
| Operating Temperature | 0°C to 70°C - commercial-grade rating suitable for industrial control panels and instrumentation |
| Propagation Delay | 15 ns typical (VCC = 5 V, CL = 15 pF) - ensures tight timing alignment in synchronous digital systems |
| Output Drive | IOL = 8 mA / IOH = –0.4 mA - directly interfaces with standard TTL and CMOS loads without buffering |
| Package | SOP (NS)-16 - surface-mount, RoHS-compliant, 1.27 mm pitch, 8.1 mm × 10.4 mm footprint |
Pinout & Package
SOP (NS)-16 package: 16-pin small-outline plastic package with gull-wing leads, 1.27 mm pitch, 8.1 mm × 10.4 mm body size, 2.00 mm max height, pin 1 index area marked on top surface.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 13 | Reset (R̅) | Active-low asynchronous reset - forces Q low and Q̅ high regardless of trigger state |
| 2, 12 | Trigger A (A) | Positive-edge sensitive input - initiates or re-triggers monostable output on rising edge |
| 3, 11 | Trigger B (B) | Negative-edge sensitive input - initiates or re-triggers monostable output on falling edge |
| 4, 10 | Timing Capacitor (CEXT) | Connects external capacitor to ground - sets pulse width with external resistor |
| 5, 9 | Timing Resistor (REXT) | Connects external resistor between VCC and CEXT pin - completes RC timing network |
| 6, 8 | Q Output | Active-high monostable output - goes high for duration tW after valid trigger |
| 7, 15 | GND | Ground reference for both sections - must be low-impedance connection |
| 14, 16 | VCC | +5 V supply - powers both monostable sections and internal logic |
| 16, 14 | Q̅ Output | Complementary active-low output - inverted timing waveform relative to Q |
Key Features
| Feature | Design Value |
|---|---|
| Retriggerable operation | Enables continuous pulse extension during ongoing trigger activity - critical for debouncing mechanical switches |
| Dual independent sections | Two fully isolated monostables in one package - reduces board space and component count vs discrete solutions |
| Edge-selectable triggering | Separate A (rising-edge) and B (falling-edge) inputs per section - supports flexible interface to diverse signal sources |
| External RC timing | Pulse width adjustable from ~20 ns to >10 s via R/C selection - accommodates microsecond to second-scale timing needs |
| LS-TTL compatibility | Input thresholds and output drive match standard 74LS family - ensures seamless integration into legacy TTL systems |
Applications
| Industrial Control Timing | Keyboard Debounce Circuit |
|---|---|
|
Use Scenario: Generating fixed-duration enable pulses for PLC I/O modules during status sampling cycles. IC Role / Device Role / Timing Role: Monostable section provides precise 100 µs strobe window synchronized to system clock edge. Use Value: Eliminates metastability in sampled inputs by guaranteeing clean, jitter-free gating windows aligned to controller timing. |
Use Scenario: Suppressing contact bounce in membrane keypads used in HMI panels. IC Role / Device Role / Timing Role: Retriggerable monostable extends output pulse beyond mechanical settling time (~20 ms). Use Value: Delivers single, clean logic transition per keypress - prevents multiple register reads or false interrupts. |
| Serial Data Pulse Shaping | Legacy Bus Arbitration Logic |
|
Use Scenario: Converting irregular RS-232 start-bit edges into uniform-width framing pulses for UART sync recovery. IC Role / Device Role / Timing Role: One section triggered by falling edge of start bit; output defines stable sample window. Use Value: Improves bit-sampling reliability in noisy environments by replacing variable edge timing with deterministic pulse width. |
Use Scenario: Implementing priority-based bus grant timeout in backplane systems using discrete TTL logic. IC Role / Device Role / Timing Role: Dual sections generate staggered arbitration windows for master/slave request resolution. Use Value: Enables deterministic, race-free bus access sequencing without microcontroller intervention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar monostable multivibrator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS123N | PDIP-16 through-hole package; identical electrical specs and timing behavior | Preferred for prototyping, breadboarding, or legacy through-hole PCBs | Select when manual assembly, socketing, or thermal testing requires leaded package |
| SN74LS123DR | SOIC-16 package with same pinout and specs; differs only in tape-and-reel packaging (2500 pcs vs 2000 pcs) | Identical functional replacement for automated SMT lines requiring different reel quantity | Choose when existing line feeders or inventory systems require SOIC-D format reels |
Compared with SN74LS123NSRG4, SN74LS123N offers mechanical robustness and hand-soldering flexibility, while SN74LS123DR provides identical SMT performance with alternate reel configuration - both preserve full timing, trigger, and drive compatibility without layout or firmware changes.
Availability
SN74LS123NSRG4 is available at Aetrix Electronics and suitable for industrial control timing, keyboard debounce circuits, serial data pulse shaping, and legacy bus arbitration logic requiring stable component supply across extended production lifecycles.
Supply support for SN74LS123NSRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial, automotive, and communications portfolio coverage.
The SN74LS123NSRG4 belongs to TI's legacy 74LS logic family, designed specifically for reliable, low-power TTL-compatible timing functions in cost-sensitive, long-lifecycle industrial and instrumentation systems.
FAQ
What is the primary function of the SN74LS123NSRG4?
The SN74LS123NSRG4 is a dual retriggerable monostable multivibrator IC that generates precise, externally adjustable output pulses in response to input triggers. Each of its two independent sections accepts rising-edge (A) or falling-edge (B) triggers and supports asynchronous reset. Its core function is timing control - extending or reshaping digital pulses in legacy TTL systems where deterministic pulse width and retrigger capability are essential.
Does the SN74LS123NSRG4 support both rising- and falling-edge triggering?
Yes, the SN74LS123NSRG4 supports dual-edge triggering per section: Trigger input A responds to rising edges, while Trigger input B responds to falling edges. This allows flexible interface with diverse signal sources - such as microcontroller GPIOs, switch closures, or asynchronous event lines - without external edge-detection circuitry. Both inputs can be used simultaneously, though only one initiates the monostable action per section.
What is the recommended external timing component range for the SN74LS123NSRG4?
The SN74LS123NSRG4 uses external R and C components to set pulse width tW ≈ 0.33 × R × C. TI specifies R ≥ 2 kΩ and C ≥ 0 pF (with practical minimum ~10 pF). Typical ranges are R = 2 kΩ–1 MΩ and C = 10 pF–100 µF, enabling pulse widths from ~20 ns to >10 seconds. For stability, use low-leakage capacitors (e.g., ceramic or film) and ensure R has ≤1% tolerance when precision timing is required.
Is the SN74LS123NSRG4 pin-compatible with other 74LS123 variants?
Yes, the SN74LS123NSRG4 shares identical pinout and electrical functionality with all 74LS123 variants in 16-pin packages - including SN74LS123N (PDIP), SN74LS123D (SOIC), and SN74LS123DR (SOIC tape-and-reel). The NS and D packages differ only in body dimensions and lead form (SOP vs SOIC), but pin numbering, signal assignment, and thermal/mounting requirements are fully aligned per JEDEC standards.
What is the operating temperature range and supply voltage specification for the SN74LS123NSRG4?
The SN74LS123NSRG4 is rated for commercial operation from 0°C to +70°C and requires a nominal +5 V supply with tolerance of 4.75 V to 5.25 V. It meets standard 74LS logic voltage thresholds: VIL ≤ 0.8 V, VIH ≥ 2.0 V, and delivers guaranteed output drive of IOL = 8 mA and IOH = –0.4 mA under these conditions - ensuring interoperability with legacy TTL and LSTTL systems.
SN74LS123NSRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LS
- Package/Case:
- 16-SOIC (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Logic Type:
- Monostable
- Independent Circuits:
- 2
- Schmitt Trigger Input:
- No
- Propagation Delay:
- 28 ns
- Current - Output High, Low:
- 400µA, 8mA
- Voltage - Supply:
- 4.75 V ~ 5.25 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
SN74LS123NSRG4 FAQ
1.How can I place an order for SN74LS123NSRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS123NSRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS123NSRG4 reliable?
The price and inventory of SN74LS123NSRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS123NSRG4 is usually 5 days.
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SN74LS123NSRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS123NSRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS123NSRG4?
For technical support, including SN74LS123NSRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS123NSRG4 requirements.
6.How does Aetrix verify that SN74LS123NSRG4 is sourced from the original manufacturer or authorized distributors?
All SN74LS123NSRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS123NSRG4 meets industry standards.
7.What is the process for return or replacement of SN74LS123NSRG4?
All SN74LS123NSRG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS123NSRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS123NSRG4 part is unused and in its original packaging.
Return procedure for SN74LS123NSRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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