Texas Instruments SN74LS125AN
- Part No.:
- SN74LS125AN
- Manufacturer:
- Texas Instruments
- Package:
- 14-DIP (0.300", 7.62mm)
- Datasheet:
-
SN74LS125AN.pdf
- Description:
- IC BUF NON-INVERT 5.25V 14DIP
- Quantity:
- Payment:

- Shipping:

Inventory:276
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Product details
Overview
SN74LS125AN from Texas Instruments is a quad 3-state bus buffer IC with independent channel enable control, designed for TTL-compatible digital bus interfacing. It features low-impedance active outputs (IOH = –1 mA, IOL = 12 mA), high-impedance off-state isolation, and operates across 0°C to 70°C in a 14-pin PDIP package. It is used in legacy industrial control backplanes and microprocessor data bus expansion.
For engineers reviewing the SN74LS125AN datasheet, SN74LS125AN pinout, SN74LS125AN application, or SN74LS125AN equivalent, key selection criteria include its active-low output enable logic, 15 ns typical propagation delay (tPLH/tPHL), 20 mA max ICC supply current, and compatibility with 5 V TTL signal levels in multi-drop bus architectures.
Technical Context
The SN74LS125AN implements four independent non-inverting buffers, each with a dedicated active-high output enable (G) input. When G is high, the output Y follows input A; when G is low, Y enters high-impedance state - enabling bidirectional bus sharing without external pull-ups.
Its LS-TTL internal circuitry uses bipolar transistor logic with Schottky clamping, delivering improved speed-power trade-offs over standard TTL: tPZH/tPZL enable/disable times of 20 ns/25 ns (CL = 5 pF), and guaranteed VOL ≤ 0.4 V at IOL = 12 mA ensure robust noise margin in loaded bus environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 4.5 V to 5.5 V - compatible with standard 5 V TTL power rails; operation outside this range risks latch-up or parameter violation. |
| Propagation Delay | 9–15 ns (tPLH/tPHL, RL = 667 Ω, CL = 45 pF) - enables reliable timing in 20–30 MHz bus clock domains with margin. |
| Output Drive | IOL = 12 mA / IOH = –1 mA - sufficient to drive 10+ standard TTL loads directly without external termination. |
| Input Thresholds | VIL = 0.7 V max, VIH = 2.0 V min - ensures clean logic level recognition across temperature and voltage variation. |
| Quiescent Current | ICC = 11–20 mA (all outputs enabled) - predictable power budgeting for legacy board-level thermal design. |
| Enable Polarity | G active-high - simplifies direct connection to microcontroller GPIO or address decoder outputs without inversion logic. |
Pinout & Package
SN74LS125AN is housed in a 14-pin plastic dual in-line package (PDIP-N), 0.300" wide, with standard through-hole mounting and RoHS-compliant NiPdAu lead finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | Output Enable (G) | Active-high control per channel; drives corresponding output into high-Z when low. |
| 2, 5, 11, 14 | Data Input (A) | Non-inverting input for each buffer channel; TTL-compatible voltage thresholds. |
| 3, 6, 12, 9 | Buffer Output (Y) | 3-state totem-pole output; low-impedance drive when enabled, high-Z when disabled. |
| 7 | GND | Signal and power ground reference for all internal logic and output stages. |
| 14 | VCC | +5 V supply rail; decoupling capacitor required within 1 cm for stable switching performance. |
Key Features
| Feature | Design Value |
|---|---|
| Independent per-channel 3-state control | Enables selective bus arbitration - only one device drives the line while others remain isolated. |
| LS-TTL compatible input/output levels | Guarantees interoperability with legacy 74LS, 74S, and 74F families without level-shifting. |
| Low static power consumption | ICC ≤ 20 mA maximum supports thermally constrained legacy PCB layouts with minimal heatsinking. |
| Robust bus drive capability | 12 mA sink current eliminates need for external pull-up resistors on shared data lines. |
Applications
| Microprocessor Data Bus Expansion | Industrial PLC Backplane Interface |
|---|---|
Use Scenario: Extending an 8-bit data bus between CPU and peripheral cards in a rack-mounted controller. IC Role / Device Role: Bidirectional bus buffer isolating CPU from add-on modules during read/write cycles. Use Value: Prevents bus contention by enabling only one module's drivers at a time via discrete G inputs tied to address decode logic. | Use Scenario: Interfacing multiple I/O modules to a central logic controller in factory automation cabinets. IC Role / Device Role: Signal conditioning and isolation layer between noisy field-side wiring and clean logic-side circuitry. Use Value: High-impedance disable state blocks ground-loop currents and prevents cross-talk between modules sharing common bus traces. |
| Legacy Test Equipment Signal Routing | EPROM Programming Adapter |
Use Scenario: Dynamically reconfiguring signal paths inside automated test fixtures using relay-matrix alternatives. IC Role / Device Role: Logic-level multiplexer substitute for routing address/data lines between DUT and tester resources. Use Value: Enables software-controlled path selection without mechanical relays - reducing wear-out and improving test cycle repeatability. | Use Scenario: Adapting vintage EPROM programmers to support different memory pinouts via configurable buffering. IC Role / Device Role: Level-translating and bus-isolating interface between programmer controller and target EPROM VPP/VCC pins. Use Value: Allows safe hot-plug insertion of EPROMs by holding outputs in high-Z until programming sequence initiates. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS126AN | Active-low output enable (G̅); identical pinout, timing, and drive specs. | Requires inverted enable signal - unsuitable where existing logic asserts high to activate buffers. | Select only if system enable logic is naturally active-low or inverters are available. |
| SN74HC125N | CMOS technology; wider VCC range (2–6 V); lower ICC (< 8 µA), but reduced drive (IOL = 7.8 mA). | Not TTL-compatible at 5 V without derating; unsuitable for legacy 74LS bus loading requirements. | Prefer only in new designs with mixed-voltage logic or ultra-low power constraints - not a drop-in replacement. |
Compared with SN74LS126AN and SN74HC125N, the SN74LS125AN provides guaranteed TTL-level drive strength and active-high enable polarity essential for direct integration into established 74LS-based systems without redesigning control logic or adding level-shifting components.
Availability
SN74LS125AN is available at Aetrix Electronics and suitable for industrial control backplanes, legacy test equipment refurbishment, and microprocessor bus expansion requiring stable component supply and long-term obsolescence mitigation.
Supply support for SN74LS125AN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic ICs for industrial, automotive, and communications markets.
The SN74LS125AN belongs to TI's legacy 74LS logic family, engineered specifically for reliable, low-cost bus interfacing in temperature-stable commercial environments (0°C to 70°C) with strict TTL compatibility.
FAQ
What is the output enable logic polarity of the SN74LS125AN?
The SN74LS125AN uses active-high output enable: when the G input is high (≥2.0 V), the Y output follows the A input; when G is low (≤0.7 V), Y enters high-impedance state. This differs from the SN74LS126AN, which uses active-low enable. The SN74LS125AN datasheet confirms G is labeled "enable" without inversion symbol, and logic diagram shows direct gating of the output stage.
Can the SN74LS125AN drive standard TTL loads directly?
Yes, the SN74LS125AN can drive up to 10 standard TTL unit loads (UL) directly: its IOL = 12 mA and IOH = –1 mA meet or exceed the 1.6 mA sink / 400 µA source requirement of a standard TTL input. No external pull-up resistors are needed on bus lines, as confirmed by the "low impedance characteristics of a TTL output" description in the SN74LS125AN datasheet.
What is the maximum operating temperature range for the SN74LS125AN?
The SN74LS125AN is rated for commercial temperature operation from 0°C to 70°C, as specified in the recommended operating conditions table of its datasheet. It is not qualified for extended industrial (–40°C to 85°C) or military (–55°C to 125°C) ranges - those require SN54LS125AJ or SNJ54LS125AJ variants.
Does the SN74LS125AN have built-in ESD protection?
The SN74LS125AN does not specify human-body model (HBM) or machine model (MM) ESD ratings in its official datasheet. As a legacy 1980s-era bipolar LS-TTL device, it lacks modern integrated ESD structures; external protection (e.g., series resistors or TVS diodes) is recommended for handling-sensitive environments. TI's packaging documentation confirms no ESD rating is assigned to the SN74LS125AN.
Is the SN74LS125AN pin-compatible with other 74-series quad buffers?
Yes, the SN74LS125AN shares identical 14-pin PDIP pinout with SN74LS126AN, SN74125N, and SN74126N - including VCC (pin 14), GND (pin 7), and channel mapping (G/A/Y per pair). However, functional compatibility requires matching enable polarity: SN74LS126AN has inverted enable logic, so direct substitution may cause incorrect bus behavior unless control signals are inverted.
SN74LS125AN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LS
- Package/Case:
- 14-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 2.6mA, 24mA
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 14-PDIP
SN74LS125AN FAQ
1.How can I place an order for SN74LS125AN through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS125AN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS125AN reliable?
The price and inventory of SN74LS125AN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS125AN is usually 5 days.
3.What payment methods are accepted for SN74LS125AN?
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4.How is shipping managed for SN74LS125AN?
SN74LS125AN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS125AN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS125AN?
For technical support, including SN74LS125AN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS125AN requirements.
6.How does Aetrix verify that SN74LS125AN is sourced from the original manufacturer or authorized distributors?
All SN74LS125AN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS125AN meets industry standards.
7.What is the process for return or replacement of SN74LS125AN?
All SN74LS125AN units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS125AN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS125AN part is unused and in its original packaging.
Return procedure for SN74LS125AN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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