onsemi SN74LS126AD
- Part No.:
- SN74LS126AD
- Manufacturer:
- onsemi
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74LS126AD.pdf
- Description:
- IC BUFF NON-INVERT 5.25V 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:30,610
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Product details
Overview
SN74LS126AD from Texas Instruments is a quad bus buffer with individual 3-state outputs, designed for TTL-compatible data bus isolation and bidirectional signal routing in legacy digital systems. It features low-power Schottky (LS) logic, 14-pin SOIC (D) package, 5 V nominal supply, and active-low output enable per channel. It enables high-impedance bus disconnection without external pullups in industrial control backplanes and vintage microprocessor address/data buses.
For engineers reviewing the SN74LS126AD datasheet, pinout, applications, or equivalent options, this page delivers verified electrical specs, true pin functions, real-world use cases, and validated alternative options - all grounded in TI's SDLS044A production data sheet and official packaging documentation.
Technical Context
The SN74LS126AD implements four independent non-inverting buffers, each with a dedicated active-low output enable (G) input. When G is low, the output Y follows input A; when G is high, Y enters high-impedance state. Its LS process ensures lower power consumption than standard TTL while maintaining compatible voltage thresholds and drive strength.
It operates across 0°C to 70°C, supports 5 V ±5% supply, and meets TTL input/output logic levels: VIH = 2 V min, VIL = 0.8 V max, VOH = 2.4 V min at –2.6 mA, VOL = 0.4 V max at 24 mA. Propagation delay is 7–15 ns typical under 5 V/25°C conditions with RL = 667 Ω and CL = 45 pF.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | 74LS (Low-Power Schottky TTL) - balances speed and power for legacy board-level integration |
| Supply Voltage | 4.75 V to 5.25 V - tight tolerance ensures stable operation in regulated 5 V rails |
| Output Drive | IOL = 24 mA max, IOH = –2.6 mA - sufficient to sink heavy bus loads without external pullups |
| Propagation Delay | tPLH/tPHL = 9–15 ns typ - enables reliable timing in 20–30 MHz bus environments |
| Enable Polarity | Active-low per channel (G input) - allows independent, asynchronous bus segment control |
| Quiescent Current | ICC = 12 mA max at VCC = 5.5 V - lower than standard 74126, reducing thermal load on dense boards |
| Input Thresholds | VIL = 0.7 V min, VIH = 2.0 V min - ensures noise margin compatibility with 74LS/74S families |
Pinout & Package
SN74LS126AD uses a 14-pin SOIC (D) package, 3.90 mm wide, 1.75 mm max height, with 1.27 mm pitch. Pin 1 is marked by a beveled corner or notch; device orientation follows JEDEC MS-012AB standard.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1G, 2G, 3G, 4G | Active-low output enable inputs | Each controls one buffer independently; low = output enabled, high = high-Z |
| 1A, 2A, 3A, 4A | Data inputs | Non-inverting inputs driving corresponding Y outputs |
| 1Y, 2Y, 3Y, 4Y | 3-state buffered outputs | Drive bus lines directly; high-Z when respective G is high |
| VCC (Pin 14) | Positive supply | 5 V DC connection; decoupling capacitor required near pin |
| GND (Pin 7) | Ground reference | Common return path for all logic and output currents |
Key Features
| Feature | Design Value |
|---|---|
| Individual channel enable | Four separate G inputs allow selective activation of bus segments without gating logic |
| High-impedance outputs | Outputs fully disconnect from bus (IOZ ≤ ±20 µA), preventing contention during multi-driver arbitration |
| TTL-compatible drive | 24 mA sink capability eliminates need for external pullup resistors on shared data/address lines |
| Low-power LS architecture | 12 mA max ICC vs. 36 mA for original 74126 - reduces board-level heat and power supply demand |
| Standard SOIC footprint | D-package (14-pin) enables drop-in replacement in existing PCB layouts designed for 74LS126A variants |
Applications
| Industrial Backplane Bus Isolation | Legacy Microprocessor Address Latching |
|---|---|
Use Scenario: Isolating multiple I/O modules on a shared 8-bit data bus in programmable logic controllers. IC Role / Device Role / Timing Role: Quad buffer provides per-module enable control, allowing only one module to drive the bus at a time. Use Value: Prevents bus contention and eliminates need for discrete pullup networks, simplifying board layout and reducing BOM count. |
Use Scenario: Latching Z80 or 8085 CPU address lines during memory-mapped peripheral access cycles. IC Role / Device Role / Timing Role: Buffers and isolates upper address bits (A8–A11) to peripheral decoders during WAIT states. Use Value: Maintains valid address hold time during bus turnaround, ensuring reliable peripheral selection without timing margin loss. |
| Test Equipment Signal Routing | EPROM Programming Interface |
Use Scenario: Switching between multiple DUT signal sources onto a common test probe line in automated test fixtures. IC Role / Device Role / Timing Role: Acts as a manual or firmware-controlled multiplexer via independent G inputs. Use Value: Enables single-probe verification of up to four devices without mechanical relays or FPGA routing overhead. |
Use Scenario: Driving 8-bit data bus between programmer controller and 27C256 EPROM during write/verify cycles. IC Role / Device Role / Timing Role: Buffers programming voltage (VPP) enable signals and data lines to meet EPROM setup/hold requirements. Use Value: Ensures clean, slew-controlled data transitions and prevents bus leakage during VPP high-voltage pulses. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS126ADR | Same die, tape-and-reel packaging (2500 pcs/reel); identical electrical specs and pinout | Preferred for automated SMT assembly; same thermal and timing behavior | Select SN74LS126ADR for volume production; SN74LS126AD is obsolete but may be available in legacy tube stock |
| SN74LS126AN | Same functionality in 14-pin PDIP (N) package; higher θJA (80°C/W vs. 86°C/W), larger footprint | Suitable for prototyping, through-hole boards, or repair of legacy equipment with DIP sockets | Choose SN74LS126AN when hand-soldering, socket-based testing, or matching original board form factor is required |
Compared with SN74LS126AD, SN74LS126ADR offers identical performance with optimized SMT logistics, while SN74LS126AN trades miniaturization for mechanical serviceability - both preserve full functional and timing equivalence in 5 V TTL systems.
Availability
SN74LS126AD is available at Aetrix Electronics and suitable for industrial backplane bus isolation, legacy microprocessor address latching, and EPROM programming interface applications requiring stable component supply and long-term obsolescence management.
Supply support for SN74LS126AD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic solutions with deep heritage in TTL and LS families.
The SN74LS126AD belongs to TI's 74LS logic product line, engineered for backward compatibility with 74-series TTL while delivering reduced power consumption and improved noise immunity in industrial and computing systems.
FAQ
What is the function of the G inputs on the SN74LS126AD?
The G inputs (pins 1, 4, 10, 13) are active-low output enable controls - one per buffer channel. When a G input is low, its corresponding Y output follows the A input; when high, the Y output enters high-impedance state. This allows independent bus segment control without external logic, making SN74LS126AD ideal for modular system designs where only one device drives the bus at a time.
Can SN74LS126AD operate at 3.3 V?
No. SN74LS126AD is specified only for 4.75 V to 5.25 V operation per TI's SDLS044A datasheet. Its input thresholds (VIH = 2.0 V min, VIL = 0.8 V max) and output drive characteristics are optimized for 5 V TTL compatibility. Using it at 3.3 V risks undefined logic states, insufficient noise margin, and failure to meet VOL/VOH specifications - SN74LS126AD must be used in 5 V systems.
Is SN74LS126AD pin-compatible with SN74LS125A?
No. While both are quad 3-state buffers in SOIC-14 packages, SN74LS126AD has active-low enables (G), whereas SN74LS125A has active-high enables (G̅). Their pinouts differ: SN74LS125A places G̅ on pins 1, 4, 10, 13 (same locations), but logic polarity reversal means direct substitution would invert enable behavior - SN74LS126AD requires complementary control signals to function correctly.
What is the maximum capacitive load SN74LS126AD can drive reliably?
Per TI's SDLS044A, SN74LS126AD is characterized for CL = 45 pF in switching tests (tPLH/tPHL). It can reliably drive up to 50 pF with minimal timing degradation; beyond that, propagation delay increases and edge rates degrade. For loads >50 pF, add series termination or reduce trace length - SN74LS126AD is not intended for transmission-line driving or high-speed clock distribution.
Does SN74LS126AD support hot insertion or live bus swapping?
No. SN74LS126AD lacks bus-hold, power-up 3-state, or Ioff protection. During power sequencing or hot insertion, unpowered VCC or floating G inputs may cause output contention or latch-up. For live-swappable applications, use modern alternatives with Ioff and power-off protection - SN74LS126AD requires controlled power-up/down and static-safe handling per MIL-STD-883.
SN74LS126AD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74LS
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 2.6mA, 24mA
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
SN74LS126AD FAQ
1.How can I place an order for SN74LS126AD through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS126AD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS126AD reliable?
The price and inventory of SN74LS126AD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS126AD is usually 5 days.
3.What payment methods are accepted for SN74LS126AD?
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4.How is shipping managed for SN74LS126AD?
SN74LS126AD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS126AD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS126AD?
For technical support, including SN74LS126AD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS126AD requirements.
6.How does Aetrix verify that SN74LS126AD is sourced from the original manufacturer or authorized distributors?
All SN74LS126AD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS126AD meets industry standards.
7.What is the process for return or replacement of SN74LS126AD?
All SN74LS126AD units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS126AD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS126AD part is unused and in its original packaging.
Return procedure for SN74LS126AD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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