Texas Instruments SN74LS126AD
- Part No.:
- SN74LS126AD
- Manufacturer:
- Texas Instruments
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74LS126AD.pdf
- Description:
- IC BUF NON-INVERT 5.25V 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:179
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Product details
Overview
SN74LS126AD from Texas Instruments is a quad bus buffer with individual 3-state outputs, designed for TTL-compatible data bus isolation and driving in industrial control and legacy computing systems. It features low-impedance active outputs (IOH = –2.6 mA, IOL = 24 mA), high-impedance disable state (IOZ ≤ ±20 µA), and active-low output enable (G low enables Y = A). It operates at VCC = 4.5–5.5 V over 0°C to 70°C.
For engineers reviewing the SN74LS126AD datasheet, SN74LS126AD pinout, SN74LS126AD application, or SN74LS126AD equivalent, key selection criteria include its active-low enable logic, LS-family propagation delay (tPLH/tPHL ≤ 15 ns), SOIC-14 package compatibility, and direct replacement suitability in 74LS bus interface designs requiring per-channel output control.
Technical Context
The SN74LS126AD implements four independent non-inverting buffers, each with a dedicated active-low output enable (G) input. When G is low, the output Y follows input A; when G is high, Y enters high-impedance state-enabling bidirectional bus sharing without external pull-ups.
Its LS-TTL circuitry delivers improved speed-power trade-off versus standard TTL: typical ICC = 12 mA at VCC = 5 V, with VOH ≥ 2.4 V at IOH = –2.6 mA and VOL ≤ 0.4 V at IOL = 24 mA. Switching performance is characterized at RL = 667 Ω and CL = 45 pF.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 4.5 V to 5.5 V - Ensures stable operation across standard TTL supply tolerances. |
| Output Drive | IOL = 24 mA / IOH = –2.6 mA - Sufficient to drive 10+ standard TTL loads without external pull-up resistors. |
| Propagation Delay | tPLH/tPHL ≤ 15 ns - Enables reliable timing in 20-MHz-class synchronous bus systems. |
| Enable Logic | Active-low G input - Allows direct connection to open-collector control lines or inverted system signals. |
| Off-State Leakage | IOZ ≤ ±20 µA - Minimizes bus loading during 3-state disable, critical for multi-driver shared buses. |
| Operating Temp | 0°C to 70°C - Qualified for commercial-grade embedded and instrumentation applications. |
Pinout & Package
SN74LS126AD is housed in a 14-pin SOIC (D) package, 3.90 mm wide, 8.65 mm long, 1.75 mm max height, with 1.27 mm pitch. Pin 1 marked by index notch or beveled corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1G, 2G, 3G, 4G | Active-low output enable inputs | Each controls one buffer channel independently; low = enabled (Y = A), high = high-Z. |
| 1A–4A | Data inputs | Non-inverting logic inputs; compatible with TTL/LS voltage thresholds (VIL ≤ 0.8 V, VIH ≥ 2 V). |
| 1Y–4Y | 3-state buffered outputs | Low-impedance push-pull when enabled; high-Z (≤ ±20 µA) when disabled. |
| VCC (Pin 14) | Positive supply | Must be decoupled locally (0.1 µF ceramic) to suppress switching noise on shared power rails. |
| GND (Pin 7) | Ground reference | Common return for all inputs, outputs, and internal logic; requires low-inductance PCB routing. |
Key Features
| Feature | Design Value |
|---|---|
| Individual per-channel 3-state control | Enables selective bus arbitration-only one device drives while others float, eliminating contention. |
| LS-TTL compatible input/output levels | Guarantees interoperability with legacy 74LS, 74S, and 74F logic families without level-shifting. |
| High sink current (24 mA) | Drives heavy capacitive loads (e.g., backplane traces, multiple TTL inputs) without external buffering. |
| Low quiescent ICC (12 mA typical) | Reduces thermal load and power supply demand in dense logic assemblies. |
| SOIC-14 surface-mount package | Supports automated assembly and higher board density than through-hole PDIP alternatives. |
Applications
| Industrial PLC Backplane Interface | Legacy Computer Memory Bus Isolation |
|---|---|
Use Scenario: Isolating CPU address/data lines from peripheral modules in modular programmable logic controllers. IC Role / Device Role / Timing Role: Quad buffer provides per-lane direction control and bus contention prevention during module hot-swap or reconfiguration. Use Value: Eliminates need for discrete pull-up resistors and reduces signal integrity risk on 100+ mm backplane traces. | Use Scenario: Separating memory controller signals from DRAM banks in 1980s-era minicomputer systems. IC Role / Device Role / Timing Role: Buffers and isolates address latches and data transceivers to prevent loading-induced timing skew. Use Value: Maintains setup/hold margins under full load (10+ TTL inputs per line) with tPLH/tPHL ≤ 15 ns. |
| Test Equipment Signal Routing Matrix | Automotive ECU Diagnostic Interface |
Use Scenario: Configurable signal path selection between DUT pins and measurement instruments in automated test fixtures. IC Role / Device Role / Timing Role: Acts as programmable signal gate-each buffer enables/disables one test channel via microcontroller GPIO. Use Value: Supports simultaneous multi-point probing with zero cross-talk due to guaranteed high-Z off-state leakage (≤ ±20 µA). | Use Scenario: Interfacing microcontroller UART and CAN controller pins to external diagnostic port connectors in early OBD-II ECUs. IC Role / Device Role / Timing Role: Level-translates and isolates debug signals while preserving TTL-compatible voltage thresholds. Use Value: Ensures robust communication over noisy vehicle harnesses using LS-TTL noise immunity (VIL = 0.8 V, VIH = 2 V). |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS126ADR | Same electrical specs and pinout; tape-and-reel packaging (2500 pcs/reel) vs. tube (SN74LS126AD). | Identical functional use; optimized for automated SMT production rather than manual prototyping. | Select SN74LS126ADR for volume manufacturing; SN74LS126AD remains viable for low-volume or repair stock. |
| SN74LS244N | Octal (8-channel) buffer with dual active-low enables (1G/2G); higher ICC (24 mA), same VCC/IO specs. | Better suited for wider buses; requires PCB layout change due to 20-pin PDIP package and different pin mapping. | Choose SN74LS244N only when expanding bus width or consolidating enable logic; not drop-in compatible. |
Compared with SN74LS126ADR, SN74LS126AD offers identical functionality in tube packaging for flexibility in small-batch builds; versus SN74LS244N, it trades channel count for pin compatibility and lower power in space-constrained 14-pin layouts.
Availability
SN74LS126AD is available at Aetrix Electronics and suitable for industrial PLC backplane interfaces, legacy computer memory bus isolation, and test equipment signal routing requiring stable component supply and long-term obsolescence management.
Supply support for SN74LS126AD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial and automotive qualification.
The SN74LS126AD belongs to TI's legacy 74LS logic family, engineered for reliability and interoperability in retro-computing, industrial control, and maintenance of aging electronic infrastructure.
FAQ
What is the output enable polarity of the SN74LS126AD?
The SN74LS126AD uses active-low output enable: each G input must be driven low to enable its corresponding Y output (Y = A); driving G high places Y in high-impedance state. This matches standard bus arbitration conventions where "enable" is asserted by ground-level signals.
Can SN74LS126AD replace SN74LS125A in an existing design?
No-SN74LS126AD has active-low enable (G low enables), while SN74LS125A has active-high enable (G high enables). Swapping them without inverting the enable signal will invert buffer behavior. The SN74LS126AD is functionally matched only to other '126-series devices like SN74LS126ADR or SN74LS126AN.
What is the maximum capacitive load the SN74LS126AD can drive reliably?
The SN74LS126AD is characterized up to CL = 45 pF with RL = 667 Ω, delivering tPLH/tPHL ≤ 15 ns. For heavier loads (>100 pF), rise/fall times degrade and may violate setup/hold timing; add series termination or reduce trace length to maintain signal integrity.
Is SN74LS126AD RoHS compliant?
SN74LS126AD is obsolete and was manufactured prior to RoHS enforcement; it contains leaded solder finish and is not RoHS compliant. For new designs, TI recommends SN74LS126ADR (RoHS-compliant, NiPdAu finish, MSL Level-1).
Does SN74LS126AD require external pull-up resistors on its outputs?
No-SN74LS126AD's totem-pole outputs provide active drive in both logic states when enabled, eliminating need for external pull-ups. Pull-ups are only required if interfacing with open-collector inputs or implementing wired-AND logic, which is outside the SN74LS126AD's intended use case.
SN74LS126AD Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LS
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 2.6mA, 24mA
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
SN74LS126AD FAQ
1.How can I place an order for SN74LS126AD through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS126AD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS126AD reliable?
The price and inventory of SN74LS126AD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS126AD is usually 5 days.
3.What payment methods are accepted for SN74LS126AD?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS126AD transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LS126AD?
SN74LS126AD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS126AD order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS126AD?
For technical support, including SN74LS126AD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS126AD requirements.
6.How does Aetrix verify that SN74LS126AD is sourced from the original manufacturer or authorized distributors?
All SN74LS126AD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS126AD meets industry standards.
7.What is the process for return or replacement of SN74LS126AD?
All SN74LS126AD units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS126AD, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS126AD part is unused and in its original packaging.
Return procedure for SN74LS126AD:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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