Texas Instruments SN74LS126ANS
- Part No.:
- SN74LS126ANS
- Manufacturer:
- Texas Instruments
- Package:
- 14-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
SN74LS126ANS.pdf
- Description:
- IC BUFFER NON-INVERT 5.25V 14SOP
- Quantity:
- Payment:

- Shipping:

Inventory:890
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Product details
Overview
SN74LS126ANS from Texas Instruments is a quad bus buffer with 3-state outputs, designed for TTL-level data bus isolation and bidirectional signal routing in legacy digital systems. It features independent low-active output enable (G) per channel, 12 mA low-level output drive, 2.4 V minimum VOH at –2.6 mA, and operates across 0°C to 70°C. Used in industrial control backplanes and vintage computer peripheral interfaces where bus contention avoidance is critical.
For engineers reviewing the SN74LS126ANS datasheet, SN74LS126ANS pinout, SN74LS126ANS application, or SN74LS126ANS equivalent, this page delivers verified electrical specs, package mapping to SOP-14 (NS), functional behavior of active-low gating, and real-world use cases in bus-hold and multiplexed address/data path designs.
Technical Context
The SN74LS126ANS implements four independent non-inverting buffers, each with a dedicated active-low 3-state output enable (G). Its logic diagram shows direct A→Y propagation when G = LOW, and high-impedance Y state when G = HIGH - distinct from the '125 family's active-high enable.
Internally, it uses LS-TTL circuitry with Schottky-clamped transistors, delivering improved speed-power trade-offs over standard TTL. Key timing parameters include tPLH/tPHL ≤15 ns (VCC = 5 V, CL = 45 pF), tPZH/tPZL ≤25 ns, and guaranteed VOL ≤0.4 V at IOL = 12 mA - enabling reliable interfacing with legacy 5 V logic families without external pull-ups.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | 74LS (Low-Power Schottky TTL), compatible with 5 V TTL/CMOS input thresholds |
| Output Type | 3-state (high-impedance), active-low enable per channel - eliminates bus conflicts during shared-line arbitration |
| Supply Voltage | 4.75–5.25 V - tight regulation required; operation outside this range risks VOH/VOL degradation |
| IOH / IOL | –2.6 mA / +12 mA - sufficient to drive 10+ TTL loads or terminate unterminated stubs on short buses |
| Propagation Delay | tPLH/tPHL ≤15 ns - supports bus clocking up to ~30 MHz in point-to-point configurations |
| Enable Timing | tPZH/tPZL ≤25 ns - ensures clean bus release before next driver activation, preventing glitches |
| Operating Temp | 0°C to 70°C - commercial-grade rating; not qualified for extended industrial or automotive environments |
Pinout & Package
SOP-14 (NS) package: 14-pin small-outline plastic package with 0.635 mm pitch, 8.1 mm × 10.4 mm body, and gull-wing leads. RoHS-compliant, tape-and-reel packaging (2000 pcs/reel), MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | Output Enable (G) | Active-low control per channel; LOW enables buffer, HIGH forces high-Z output |
| 2, 5, 9, 12 | Data Input (A) | TTL-compatible input; VIH ≥2 V, VIL ≤0.8 V - matches standard 5 V logic thresholds |
| 3, 6, 8, 11 | Buffered Output (Y) | Non-inverting 3-state output; drives bus lines directly without external pull-up resistors |
| 7 | GND | Ground reference for all internal circuitry and output stage return path |
| 14 | VCC | +5 V supply; decoupling capacitor (0.1 µF ceramic) required within 10 mm of pin |
Key Features
| Feature | Design Value |
|---|---|
| Independent per-channel enable | Four separate G inputs allow selective activation of individual bus segments without affecting others |
| High-impedance off-state | IOZ ≤ ±20 µA ensures negligible loading on shared bus lines during disable - prevents signal corruption |
| LS-TTL drive capability | 12 mA sink current supports direct connection to 10+ standard TTL inputs - eliminates need for external drivers |
| Guaranteed switching performance | Specified tPLH/tPHL ≤15 ns at 5 V/25°C ensures predictable timing margins in synchronous bus architectures |
| Legacy system compatibility | PIN-compatible with SN74LS126AN (PDIP) and SN74LS126ADR (SOIC) - enables drop-in replacement in existing layouts |
Applications
| Industrial Backplane Bus Isolation | Vintage Computer Peripheral Interface |
|---|---|
Use Scenario: Isolating CPU address/data bus from multiple expansion cards in programmable logic controllers. IC Role / Device Role / Timing Role: Quad buffer acts as bi-directional bus gate, enabling one card at a time while presenting high-Z to others. Use Value: Prevents bus contention during hot-swap or multi-master arbitration; eliminates need for discrete bus transceivers. | Use Scenario: Interfacing Z80-based S-100 bus peripherals with memory-mapped I/O registers. IC Role / Device Role / Timing Role: Buffers address latches and data strobes with precise enable timing to meet S-100 setup/hold requirements. Use Value: Meets tPZH ≤25 ns spec to ensure clean bus release before next cycle - avoids read/write corruption. |
| Test Equipment Signal Routing | Legacy Instrumentation Data Multiplexing |
Use Scenario: Routing DUT signals through automated test fixtures with selectable path configuration. IC Role / Device Role / Timing Role: Acts as programmable signal switch; G inputs controlled by microcontroller GPIOs. Use Value: Active-low enable simplifies firmware logic (LOW = pass-through); 12 mA drive handles fixture cabling capacitance. | Use Scenario: Multiplexing analog-to-digital converter outputs onto a shared 8-bit parallel bus in data loggers. IC Role / Device Role / Timing Role: Buffers ADC parallel output bits; G pins synchronized to conversion completion pulse. Use Value: Guaranteed VOL ≤0.4 V at 12 mA ensures noise margin >0.4 V against TTL logic thresholds - improves measurement reliability. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS126AN | Same logic function and specs, but in 14-pin PDIP (N) package - larger footprint, through-hole mounting | Preferred for prototyping, repair of legacy PCBs, or sockets requiring DIP form factor | Select SN74LS126AN when board layout uses through-hole pads or requires manual reworkability. |
| SN74LS126ADR | Identical electrical specs and SOP-14 (D) package - differs only in lead finish (NIPDAU) and reel quantity (2500 vs 2000) | Functionally interchangeable; used in high-volume surface-mount production with different tape specifications | Choose SN74LS126ADR for automated assembly lines using standard SOIC carrier tape configurations. |
Compared with SN74LS126AN and SN74LS126ADR, the SN74LS126ANS offers identical logic behavior and timing in a SOP-14 (NS) package optimized for compact layouts and cost-sensitive volume production - differing only in mechanical dimensions and packaging format, not functionality.
Availability
SN74LS126ANS is available at Aetrix Electronics and suitable for industrial backplane bus isolation, vintage computer peripheral interface, and test equipment signal routing requiring stable component supply across long-lifecycle embedded programs.
Supply support for SN74LS126ANS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial and automotive qualification.
The SN74LS126ANS belongs to TI's legacy 74LS logic family, engineered for robust 5 V TTL interoperability in mission-critical industrial control and retrocomputing applications where long-term part availability and proven reliability are essential.
FAQ
What is the output enable polarity of the SN74LS126ANS?
The SN74LS126ANS features active-low output enable (G) inputs: each channel's output Y is enabled (driving A) when its corresponding G pin is LOW, and enters high-impedance state when G is HIGH. This differs from the '125 family, which uses active-high enable - correct polarity is essential for proper bus arbitration in the SN74LS126ANS.
Can SN74LS126ANS replace SN74LS126AN in an existing design?
Yes, the SN74LS126ANS can replace SN74LS126AN electrically and functionally, as both share identical logic behavior, timing, and DC specs. However, the SN74LS126ANS uses SOP-14 (NS) packaging versus PDIP-14 (N), requiring PCB layout revision for surface-mount assembly - no changes to firmware or schematic logic are needed for the SN74LS126ANS.
What is the maximum capacitive load the SN74LS126ANS can drive reliably?
The SN74LS126ANS is characterized for CL = 45 pF in switching tests (tPLH/tPHL ≤15 ns), and supports stable operation up to 50 pF with minor timing degradation. For loads exceeding 50 pF, series termination or reduced edge rates are recommended - the SN74LS126ANS does not specify performance beyond 50 pF in official characterization.
Does SN74LS126ANS support mixed-voltage interfacing (e.g., 3.3 V inputs)?
No, the SN74LS126ANS is a 5 V-only TTL device: VIH = 2.0 V minimum and VIL = 0.8 V maximum assume 5 V rail operation. Driving it with 3.3 V logic may result in marginal or non-functional high-level recognition; level-shifting is required for reliable 3.3 V → SN74LS126ANS interfacing.
Is SN74LS126ANS suitable for automotive applications?
No, the SN74LS126ANS is rated for 0°C to 70°C operation and carries no AEC-Q200 qualification. It lacks automotive-grade screening, extended temperature support, or enhanced ESD robustness - use only in commercial or industrial environments. Automotive alternatives require explicit Q-grade part numbers, not the SN74LS126ANS.
SN74LS126ANS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LS
- Package/Case:
- 14-SOIC (0.209", 5.30mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 5.2mA, 16mA
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SO
SN74LS126ANS FAQ
1.How can I place an order for SN74LS126ANS through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS126ANS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS126ANS reliable?
The price and inventory of SN74LS126ANS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS126ANS is usually 5 days.
3.What payment methods are accepted for SN74LS126ANS?
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4.How is shipping managed for SN74LS126ANS?
SN74LS126ANS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS126ANS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS126ANS?
For technical support, including SN74LS126ANS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS126ANS requirements.
6.How does Aetrix verify that SN74LS126ANS is sourced from the original manufacturer or authorized distributors?
All SN74LS126ANS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS126ANS meets industry standards.
7.What is the process for return or replacement of SN74LS126ANS?
All SN74LS126ANS units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS126ANS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS126ANS part is unused and in its original packaging.
Return procedure for SN74LS126ANS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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