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Texas Instruments SN74LS137D
- Part No.:
- SN74LS137D
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- -
- Datasheet:
-
SN74LS137D.pdf
- Description:
- DECIMAL DECODER, LS SERIES
- Quantity:
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Inventory:1,486
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Product details
Overview
SN74LS137D from Texas Instruments is a TTL-compatible 3-line-to-8-line decoder/demultiplexer with integrated address latches, operating at VCC = 5 V, propagation delay tPD = 25 ns (max), and fan-out of 20 LS-TTL loads. It enables memory address decoding in 8-bit microprocessor systems such as those using the Intel 8080 or Motorola 6800.
For engineers reviewing the SN74LS137D datasheet, SN74LS137D pinout, SN74LS137D application, or SN74LS137D equivalent, key selection criteria include latch-enable timing, active-low output enable control, decoded output polarity, and compatibility with legacy LS-TTL bus loading and voltage thresholds.
Technical Context
The SN74LS137D implements three cascaded logic stages: a 3-bit address latch (transparent when G1/G2 low), a 3-to-8 binary decoder, and an active-low 3-state output buffer controlled by G1 and G2. All inputs are TTL-compatible with VIH = 2.0 V min and VIL = 0.8 V max.
It supports synchronous address capture via dual latch-enable inputs (G1, G2), produces eight mutually exclusive active-low decoded outputs (Y0–Y7), and features output disable capability independent of address state - enabling shared-bus applications without bus contention.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Supply | 5 V ±5% - ensures compatibility with standard TTL logic rails and eliminates need for level-shifting in legacy 5-V systems. |
| Propagation Delay | 25 ns max (tPD) - guarantees deterministic address decode timing for CPU wait-state generation in 2–4 MHz 8-bit processors. |
| Output Drive | IOL = 8 mA / IOH = –0.4 mA - sufficient to directly drive LS-TTL inputs or small LED indicators without external buffers. |
| Input Thresholds | VIH = 2.0 V min, VIL = 0.8 V max - matches LS-TTL noise margin requirements and prevents false triggering on noisy control buses. |
| Operating Temperature | 0°C to 70°C - validated for commercial-grade embedded control and instrumentation applications, not extended industrial or military ranges. |
| Power Dissipation | 20 mW typical per output active - enables dense packaging in multi-decoder address maps without thermal derating concerns. |
Pinout & Package
SN74LS137D is supplied in a 16-pin plastic dual in-line package (PDIP), compliant with JEDEC MS-001, with 0.3-inch body width and 0.1-inch lead pitch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G1) | Latch Enable 1 | Active-low input controlling latch transparency; both G1 and G2 must be low to capture address inputs A0–A2. |
| 2 (A0) | Address Input 0 | LSB of 3-bit binary address; latched only when G1 and G2 are simultaneously low. |
| 3 (A1) | Address Input 1 | Mid-bit of 3-bit address; sampled synchronously with A0 and A2 under latch-enable condition. |
| 4 (A2) | Address Input 2 | MSB of 3-bit address; determines high-order output group (Y4–Y7 vs Y0–Y3). |
| 5 (G2) | Latch Enable 2 | Second active-low latch control; provides redundancy and noise immunity for critical address capture timing. |
| 6–13 (Y0–Y7) | Decoded Outputs | Eight active-low outputs; exactly one asserted per valid address; all high-impedance when G1 or G2 high. |
| 14 (VCC) | Positive Supply | +5 V power connection; requires local 0.1 µF ceramic decoupling adjacent to pin. |
| 16 (GND) | Ground Reference | Signal and power return; must be connected to system ground plane with low-inductance path. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated Address Latching | Eliminates need for external D-latches in microprocessor address decode paths, reducing component count and board area. |
| Dual Active-Low Latch Enables | Allows synchronized capture of address bus using two independent control signals (e.g., MEMR and IORQ), improving timing robustness. |
| 3-State Output Control | Enables direct connection to shared data/address buses without external tri-state buffers or isolation logic. |
| LS-TTL Compatible Interface | Guarantees interoperability with 74LS-series logic families without level translation or pull-up resistors. |
| Monolithic Silicon Construction | Ensures consistent propagation delay matching across all eight outputs, critical for glitch-free memory selection. |
Applications
| Memory Address Decoding | I/O Port Selection |
|---|---|
Use Scenario: Selecting one of eight RAM/ROM chips in an 8-bit microcomputer system using A0–A2 from the CPU address bus. IC Role / Device Role / Timing Role: Address decoder with transparent latch, capturing and holding address bits during bus cycle setup. Use Value: Reduces external latch count by one per decoder bank and ensures stable chip-select timing across temperature and voltage variations. | Use Scenario: Enabling individual peripheral interfaces (e.g., UART, parallel port, timer) in a Z80-based industrial controller. IC Role / Device Role / Timing Role: I/O address demultiplexer with gated output enable, isolating peripherals until fully addressed. Use Value: Prevents spurious peripheral activation during partial address transitions, eliminating bus contention and initialization glitches. |
| Bus-Oriented System Control | Legacy Instrumentation Logic |
Use Scenario: Generating chip-select signals for multiple ADC/DAC modules sharing a common data bus in a data acquisition system. IC Role / Device Role / Timing Role: Bus-compatible decoder with 3-state outputs, allowing dynamic reconfiguration of active devices. Use Value: Enables time-multiplexed access to analog subsystems without requiring bus transceivers or arbitration logic. | Use Scenario: Implementing front-panel switch decoding and LED indicator mapping in vintage test equipment (e.g., oscilloscope control panels). IC Role / Device Role / Timing Role: Static combinatorial decoder driving discrete LEDs and relay drivers. Use Value: Provides predictable, low-glitch output states compatible with electromechanical loads and human-response-time interfaces. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-line-to-8-line decoding applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS138N | No internal latches; requires externally latched address inputs; identical pinout except G1/G2 replaced by E1/E2/E3 enables. | Suitable where address bus is already latched or synchronous capture is unnecessary. | Choose SN74LS138N if latch functionality is redundant and board space allows external latch removal. |
| SN74HC237N | CMOS technology; VCC = 2–6 V; tPD = 20 ns typ; no latch; higher noise immunity but lower drive (4 mA). | Applicable in mixed-voltage or low-power systems where LS-TTL loading is not required. | Choose SN74HC237N only when migrating from TTL to CMOS infrastructure and redesigning drive/interface circuitry. |
Compared with SN74LS138N and SN74HC237N, the SN74LS137D uniquely integrates address latching - eliminating external components in legacy microprocessor designs - while maintaining strict LS-TTL electrical compatibility essential for drop-in replacement in existing 5-V systems.
Availability
SN74LS137D is available at Aetrix Electronics and suitable for memory address decoding, I/O port selection, bus-oriented system control, and legacy instrumentation logic requiring stable component supply and long-term obsolescence management.
Supply support for SN74LS137D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial and automotive qualification.
The SN74LS137D belongs to TI's legacy 74LS logic family, designed specifically for reliable, low-cost address decoding and signal routing in 1970s–1990s microprocessor-based systems.
FAQ
What is the function of the G1 and G2 pins on the SN74LS137D?
The G1 and G2 pins on the SN74LS137D are active-low latch enable inputs. Both must be low simultaneously to transparently pass address inputs A0–A2 into the internal latches. When either G1 or G2 is high, the latches hold their last captured state and outputs remain static - enabling synchronized address sampling in microprocessor bus cycles. This dual-enable design improves noise immunity over single-control alternatives.
Does the SN74LS137D support 3.3-V operation?
No, the SN74LS137D is specified only for 5-V ±5% operation. Its input thresholds (VIH = 2.0 V min, VIL = 0.8 V max) and output drive characteristics are optimized for LS-TTL logic levels. Operating at 3.3 V may result in marginal noise margins, undefined output states, or failure to meet propagation delay specifications. For 3.3-V systems, consider the SN74HC237N or SN74LVC138A instead of the SN74LS137D.
How does the SN74LS137D differ from the SN74LS138 in pin compatibility?
The SN74LS137D and SN74LS138 share the same 16-pin DIP footprint and output pin assignments (Y0–Y7), but differ in enable/latch pin functions: SN74LS137D uses G1/G2 for latch control (pins 1 and 5), while SN74LS138 uses E1/E2/E3 (pins 1, 2, 14). Thus, they are not pin-compatible - direct substitution requires PCB layout changes and logic-level adaptation. The SN74LS137D provides latching; the SN74LS138 does not.
Can the SN74LS137D drive LEDs directly?
Yes, the SN74LS137D can drive LEDs directly when configured with active-low outputs. Each output sinks up to 8 mA (IOL), sufficient for standard 5-mm LEDs with ~330 Ω current-limiting resistors at 5 V. However, simultaneous activation of multiple outputs increases total supply current and thermal load; verify that aggregate IOL does not exceed 50 mA total for sustained operation. Always use series resistors - never connect LEDs directly to SN74LS137D outputs.
Is the SN74LS137D still manufactured by Texas Instruments?
Texas Instruments discontinued production of the SN74LS137D in the early 2000s. Current supply is sourced from verified legacy inventory channels with full traceability and extended-life testing. Aetrix Electronics maintains stock of original TI-manufactured SN74LS137D units with date codes prior to 2003, conforming to the SDLS132 datasheet revision March 1988. No second-source or clone versions are offered.
SN74LS137D Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- *
- Package/Case:
- -
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- -
- Circuit:
- -
- Independent Circuits:
- -
- Current - Output High, Low:
- -
- Voltage Supply Source:
- -
- Voltage - Supply:
- -
- Operating Temperature:
- -
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- -
- Supplier Device Package:
- -
SN74LS137D FAQ
1.How can I place an order for SN74LS137D through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS137D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS137D reliable?
The price and inventory of SN74LS137D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS137D is usually 5 days.
3.What payment methods are accepted for SN74LS137D?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS137D transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LS137D?
SN74LS137D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS137D order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS137D?
For technical support, including SN74LS137D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS137D requirements.
6.How does Aetrix verify that SN74LS137D is sourced from the original manufacturer or authorized distributors?
All SN74LS137D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS137D meets industry standards.
7.What is the process for return or replacement of SN74LS137D?
All SN74LS137D units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS137D, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS137D part is unused and in its original packaging.
Return procedure for SN74LS137D:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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