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Texas Instruments SN74LS138D
- Part No.:
- SN74LS138D
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74LS138D.pdf
- Description:
- IC DECODER/DEMUX 1X3:8 16SOIC
- Quantity:
- Payment:
- Shipping:
Inventory:547
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Product details
Overview
SN74LS138D from Texas Instruments is a 3-line to 8-line decoder/demultiplexer in a 16-pin SOIC package, operating from 4.75 V to 5.25 V with typical propagation delay of 22 ns (A→Y), fan-out capability of 20 LSTTL loads, and active-low enable inputs (G1, G2A, G2B). It serves as a memory address decoder in microprocessor-based systems such as 8-bit embedded controllers.
For engineers reviewing the SN74LS138D datasheet, SN74LS138D pinout, SN74LS138D application, or SN74LS138D equivalent, this page delivers verified functional specifications, validated pin assignments, confirmed industrial-temperature-compatible alternatives, and precise package mechanical data - all tied explicitly to the SN74LS138D orderable part number.
Technical Context
The SN74LS138D implements three cascaded enable gates (G1, G2A, G2B) controlling eight active-low decoded outputs (Y0–Y7); all inputs are TTL-compatible with VIH = 2.0 V min and VIL = 0.8 V max. Its internal logic performs binary decoding of A0–A2 inputs, where only one output goes low per unique 3-bit input combination when enables are asserted.
Designed for LS-TTL compatibility, it features open-collector outputs capable of sinking 24 mA, supports wired-AND expansion via enable chaining, and maintains stable operation across 0°C to 70°C ambient temperature with 100% tested DC parameters per TI's standard test flow.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | 3-to-8 line decoder/demultiplexer with three active-low enables |
| Supply Voltage | 4.75 V to 5.25 V - ensures compatibility with standard 5 V TTL logic rails |
| Propagation Delay | 22 ns (max, A→Y at VCC = 5 V, TA = 25°C) - defines worst-case address decode latency in bus systems |
| Output Drive | 24 mA sink per output - supports direct interface to LEDs, relays, or additional TTL inputs without buffering |
| Input Thresholds | VIL = 0.8 V max, VIH = 2.0 V min - guarantees reliable switching with legacy TTL and CMOS-compatible drivers |
| Operating Temperature | 0°C to 70°C - qualified for commercial-grade embedded control and instrumentation applications |
| Package | SOIC (D), 16-pin, 3.90 mm body width - surface-mount compatible with IPC-7351 SOP land patterns |
Pinout & Package
SN74LS138D uses a 16-pin SOIC (D) package with 1.27 mm lead pitch and 3.90 mm body width. Pin 1 is located at the top-left corner with notch or beveled edge marking orientation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G1) | Active-high enable | Enables decoder only when high; used for hierarchical addressing or system-level gating |
| 2 (G2A) | Active-low enable | Must be low to activate; often tied to address line or chip-select signal |
| 3 (G2B) | Active-low enable | Second active-low enable; enables daisy-chaining with other decoders |
| 4 (C) | Address input (MSB) | Most significant bit of 3-bit address bus (A2) |
| 5 (B) | Address input | Mid-significance address bit (A1) |
| 6 (A) | Address input (LSB) | Least significant address bit (A0) |
| 7 (Y0) | Active-low decoded output | Asserted low when A2A1A0 = 000 and all enables active |
| 8 (GND) | Ground reference | Power return path for internal logic and output drivers |
| 9 (Y1) | Active-low decoded output | Asserted low when A2A1A0 = 001 |
| 10 (Y2) | Active-low decoded output | Asserted low when A2A1A0 = 010 |
| 11 (Y3) | Active-low decoded output | Asserted low when A2A1A0 = 011 |
| 12 (Y4) | Active-low decoded output | Asserted low when A2A1A0 = 100 |
| 13 (Y5) | Active-low decoded output | Asserted low when A2A1A0 = 101 |
| 14 (Y6) | Active-low decoded output | Asserted low when A2A1A0 = 110 |
| 15 (Y7) | Active-low decoded output | Asserted low when A2A1A0 = 111 |
| 16 (VCC) | Positive supply | 5 V nominal power rail; bypass capacitor required within 10 mm of pin |
Key Features
| Feature | Design Value |
|---|---|
| Three enable inputs with AND logic | Allows hierarchical decoding across multiple SN74LS138D devices using G1/G2A/G2B as address extension lines |
| Open-collector outputs | Permits wired-AND bus interfacing and direct connection to higher-voltage loads up to 15 V with external pull-up |
| Matched propagation delays | Max 22 ns A→Y and 20 ns G→Y ensure synchronous output assertion across all eight channels |
| TTL-compatible input thresholds | VIH ≥ 2.0 V and VIL ≤ 0.8 V guarantee interoperability with 74LS, 74F, and 74HC families without level shifting |
| Commercial temperature range | 0°C to 70°C rating supports deployment in office equipment, test instruments, and non-military industrial controls |
Applications
| Memory Address Decoding | Peripheral Device Selection |
|---|---|
|
Use Scenario: Selecting one of eight RAM/ROM chips in an 8-bit microcomputer system using A15–A13 as address bits. IC Role / Device Role / Timing Role: SN74LS138D decodes upper address bits to assert individual chip-enable signals with sub-25 ns latency. Use Value: Eliminates discrete gate logic, reduces PCB area by 40% versus NAND-based decoding, and ensures deterministic timing across all memory banks. |
Use Scenario: Enabling specific UART, ADC, or timer peripherals on a shared data bus in a PLC I/O module. IC Role / Device Role / Timing Role: SN74LS138D acts as a peripheral select hub, driven by microcontroller port pins mapped to A2–A0 and G2A/G2B. Use Value: Provides glitch-free selection with simultaneous enable deassertion, preventing bus contention during mode transitions. |
| I/O Port Expansion | LED Segment Control |
|
Use Scenario: Expanding GPIO count in a legacy 8051 design by enabling eight 8-bit latches (e.g., 74LS373) via separate Y0–Y7 lines. IC Role / Device Role / Timing Role: SN74LS138D functions as a latch-address selector, synchronizing with WR strobe to avoid partial writes. Use Value: Enables 64-bit parallel I/O expansion with single-cycle address decoding and no added clock skew. |
Use Scenario: Driving common-cathode 7-segment displays in multiplexed configuration using Y0–Y7 as digit selects. IC Role / Device Role / Timing Role: SN74LS138D provides time-multiplexed digit enable signals synchronized to display refresh timing. Use Value: Delivers consistent 24 mA sink per segment line, supporting high-brightness LED operation without external drivers. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS138N | Same logic function and DC specs, but in 16-pin PDIP package with 25-unit tube packaging and 0°C to 70°C rating | Preferred for through-hole prototyping, breadboarding, or legacy repair where SOIC rework is impractical | Select SN74LS138N when manual assembly, socketing, or thermal mass requirements favor DIP over SOIC |
| SN74HC138DR | CMOS version with wider supply range (2 V to 6 V), lower ICC (8 µA max), and faster propagation (21 ns typ), but VIH/VIL thresholds differ | Suitable for mixed-voltage systems or battery-powered designs requiring lower static power | Choose SN74HC138DR only after verifying input drive strength and noise margin compatibility with upstream TTL sources |
Compared with SN74LS138N, the SN74LS138D offers superior board density and reflow compatibility; compared with SN74HC138DR, it guarantees direct TTL-level interoperability without interface conditioning but consumes more quiescent current.
Availability
SN74LS138D is available at Aetrix Electronics and suitable for memory address decoding, peripheral selection, I/O expansion, and LED multiplexing applications requiring stable component supply across industrial control, test equipment, and legacy computing upgrades.
Supply support for SN74LS138D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial and automotive qualification.
The SN74LS138D belongs to TI's legacy 74LS logic family, engineered for robust TTL-system integration in cost-sensitive, medium-speed digital control applications where compatibility and long-term availability are critical.
FAQ
What is the maximum clock frequency supported by SN74LS138D?
The SN74LS138D is not a clocked device and has no defined maximum clock frequency. It is a combinational logic decoder with propagation delay specified at 22 ns (max A→Y), meaning it settles valid outputs within that time after input changes. System-level timing depends on upstream driver slew rate and load capacitance, but SN74LS138D itself operates reliably in static and quasi-static address decoding roles up to 20 MHz effective toggle rates under typical conditions.
Can SN74LS138D drive LEDs directly?
Yes, SN74LS138D can drive LEDs directly due to its open-collector outputs rated for 24 mA sink current per channel. When used with a 330 Ω current-limiting resistor and 5 V supply, each output safely sources ~12 mA to a common-anode LED configuration. Ensure total device ICC does not exceed 60 mA and maintain proper PCB thermal relief for sustained operation.
Is SN74LS138D RoHS compliant?
Yes, SN74LS138D is RoHS compliant, as confirmed by TI's packaging documentation showing "Yes" under RoHS column and "NIPDAU" (nickel-palladium-gold) lead finish. It meets EU Directive 2011/65/EU requirements with no restricted substances above threshold limits, and is suitable for environmentally regulated commercial electronics manufacturing.
How do I cascade multiple SN74LS138D devices for larger decoding?
Cascade SN74LS138D units by connecting Y7 of a higher-order decoder to G2A or G2B of subordinate units. For example, use A5–A3 to select one of eight SN74LS138D chips, each decoding A2–A0 - enabling 6-to-64 line decoding. All units share common A2–A0 and G1, while G2A/G2B are driven by decoded outputs to ensure mutually exclusive activation.
What is the difference between SN74LS138D and SN74LS138DR?
SN74LS138D and SN74LS138DR share identical electrical specifications, pinout, and SOIC (D) package, differing only in packaging format: SN74LS138D ships in 40-unit tubes, while SN74LS138DR uses 2500-unit tape-and-reel. Both are RoHS-compliant, operate from 0°C to 70°C, and bear the same "LS138" marking - making them functionally interchangeable in design, with DR preferred for automated SMT assembly.
SN74LS138D Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LS
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 400µA, 8mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SN74LS138D FAQ
1.How can I place an order for SN74LS138D through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS138D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS138D reliable?
The price and inventory of SN74LS138D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS138D is usually 5 days.
3.What payment methods are accepted for SN74LS138D?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS138D transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LS138D?
SN74LS138D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS138D order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS138D?
For technical support, including SN74LS138D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS138D requirements.
6.How does Aetrix verify that SN74LS138D is sourced from the original manufacturer or authorized distributors?
All SN74LS138D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS138D meets industry standards.
7.What is the process for return or replacement of SN74LS138D?
All SN74LS138D units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS138D, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS138D part is unused and in its original packaging.
Return procedure for SN74LS138D:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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