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Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments SN74LS138NSR

Name: SN74LS138NSR
Brand: Texas Instruments
SKU: SN74LS138NSR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74LS138NSR

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: 16-SOIC (0.209", 5.30mm Width)

Datasheet:: SN74LS138NSR.pdf

Description:: IC DECODER/DEMUX 1 X 3:8 16SO

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Product details

Overview

SN74LS138NSR from Texas Instruments is a 3-line-to-8-line decoder/demultiplexer in a 16-pin SOP (NS) package, operating from 4.75 V to 5.25 V with typical propagation delay of 22 ns at V_CC = 5 V and T_A = 25 °C. It features three enable inputs (G1, G2A, G2B) and eight active-low decoded outputs (Y0–Y7), used for address decoding in microprocessor systems and memory selection.

For engineers reviewing the SN74LS138NSR datasheet, SN74LS138NSR pinout, SN74LS138NSR application, or SN74LS138NSR equivalent, this page delivers verified electrical parameters, package dimensions, functional role in bus decoding, and validated drop-in alternatives for industrial control and legacy TTL logic upgrades.

Technical Context

The SN74LS138NSR implements standard TTL-compatible logic with Schottky-clamped bipolar transistors, supporting fan-out of 20 LS-TTL loads. Its decoding function maps binary inputs A0–A2 to one of eight mutually exclusive low-active outputs when all enables are asserted.

Enable logic requires G1 high and both G2A and G2B low for output activation; all outputs remain high otherwise. Input thresholds meet standard LS-TTL specifications: V_IL ≤ 0.8 V, V_IH ≥ 2.0 V, ensuring interoperability with 74LS, 74S, and 74F families in mixed-logic designs.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	4.75 V to 5.25 V - ensures stable operation within standard 5 V TTL supply tolerance.
Propagation Delay	22 ns max (A→Y, G→Y) - determines maximum clock rate for address decode in 8-bit systems.
Output Drive	I_OL = 8 mA, I_OH = –0.4 mA - supports direct interface to LS-TTL inputs without pull-up resistors.
Input Thresholds	V_IL ≤ 0.8 V, V_IH ≥ 2.0 V - guarantees reliable logic level recognition across temperature and voltage variation.
Operating Temp	0 °C to 70 °C - qualified for commercial-grade embedded control and instrumentation applications.
Package	SOP (NS), 16-pin, 1.27 mm pitch - surface-mount compatible with standard reflow profiles (Level-1-260°C-UNLIM).

Pinout & Package

SOP (NS) package: 16-pin small-outline package with 1.27 mm lead pitch, 10.4 mm × 5.3 mm body, and maximum height of 2.00 mm. RoHS-compliant NiPdAu lead finish, tape-and-reel packaging (2000 units/reel), Q1 pin-1 quadrant orientation.

Pin/Terminal	Circuit Role	Design Meaning
1 (G2A)	Active-low enable input	Must be low to activate decoder; tied to ground or system enable signal.
2 (G2B)	Active-low enable input	Second low-enable; often connected with G2A for synchronous gating.
3 (G1)	Active-high enable input	High enables decoding; used for hierarchical chip select in multi-chip systems.
4 (C)	MSB address input	Most significant bit of 3-bit address bus; determines Y4–Y7 vs Y0–Y3 group.
5 (B)	Address input	Mid-significance bit; combined with A and C to uniquely select one of eight outputs.
6 (A)	LSB address input	Least significant bit; completes 3-bit binary input mapping to Y0–Y7.
7 (Y0)	Active-low decoded output	Asserted low when A=B=C=0 and all enables active; drives select line for device 0.
8 (GND)	Ground reference	Power return path; must be low-impedance connection for noise immunity.
9 (Y1)	Active-low decoded output	Asserted low for A=1, B=C=0; used for peripheral #1 selection in memory-mapped I/O.
10 (Y2)	Active-low decoded output	Asserted low for A=0, B=1, C=0; enables second peripheral or memory bank.
11 (Y3)	Active-low decoded output	Asserted low for A=B=1, C=0; commonly assigned to UART or timer peripheral.
12 (Y4)	Active-low decoded output	Asserted low for C=1, A=B=0; selects higher-address peripherals or expansion slots.
13 (Y5)	Active-low decoded output	Asserted low for C=1, A=1, B=0; used in multi-layer address decoding trees.
14 (Y6)	Active-low decoded output	Asserted low for C=1, A=0, B=1; supports up to eight discrete device selections.
15 (Y7)	Active-low decoded output	Asserted low only when A=B=C=1; final output in full 3-to-8 decode sequence.
16 (V_CC)	Positive supply	5 V nominal power rail; requires local 0.1 µF ceramic decoupling adjacent to pin.

Key Features

Feature	Design Value
Three enable inputs	Enables hierarchical decoding: G1 (high-enable) + G2A/G2B (low-enable) allow cascading with other SN74LS138NSR devices.
Active-low outputs	Direct compatibility with common cathode LED displays and NMOS/CMOS enable inputs requiring low-level assertion.
TTL-compatible thresholds	V_IL/V_IH margins ensure robust noise immunity in industrial environments with ±0.4 V noise margin.
22 ns propagation delay	Supports address decode in 8-bit microcontrollers running at ≤20 MHz system clocks.
SOP (NS) packaging	Surface-mount form factor reduces PCB area by >50% vs PDIP, enabling compact industrial controller designs.

Applications

Memory Address Decoding	Peripheral Selection
Use Scenario: Selecting one of eight RAM/ROM chips in an 8085-based embedded system using A0–A2 and chip-select lines. IC Role / Device Role / Timing Role: SN74LS138NSR acts as primary address decoder, translating 3-bit segment offset into individual chip-enable signals. Use Value: Eliminates discrete NAND gate networks, reducing component count and board space while maintaining deterministic 22 ns decode latency.	Use Scenario: Assigning unique I/O addresses to UART, timer, and GPIO expanders on an ISA-style backplane. IC Role / Device Role / Timing Role: SN74LS138NSR provides synchronized peripheral enable strobes under CPU address and control bus timing. Use Value: Ensures glitch-free selection during address setup/hold windows, preventing spurious peripheral access.
Bus Multiplexing	Logic State Machine Control
Use Scenario: Routing data between multiple sensors and a single ADC channel in a PLC analog input module. IC Role / Device Role / Timing Role: SN74LS138NSR functions as an 8:1 demultiplexer, steering sensor outputs based on controller address bits. Use Value: Enables time-division sampling of eight channels with no external switching transistors or timing overhead.	Use Scenario: Generating state-specific control signals (e.g., reset, load, shift) in a 3-bit finite-state machine for motor sequencing. IC Role / Device Role / Timing Role: SN74LS138NSR converts current state register output into discrete active-low control lines. Use Value: Replaces complex PAL programming with fixed, predictable, and radiation-tolerant TTL logic for safety-critical sequences.

Memory Address Decoding

Peripheral Selection

Use Scenario: Selecting one of eight RAM/ROM chips in an 8085-based embedded system using A0–A2 and chip-select lines.

IC Role / Device Role / Timing Role: SN74LS138NSR acts as primary address decoder, translating 3-bit segment offset into individual chip-enable signals.

Use Value: Eliminates discrete NAND gate networks, reducing component count and board space while maintaining deterministic 22 ns decode latency.

Use Scenario: Assigning unique I/O addresses to UART, timer, and GPIO expanders on an ISA-style backplane.

IC Role / Device Role / Timing Role: SN74LS138NSR provides synchronized peripheral enable strobes under CPU address and control bus timing.

Use Value: Ensures glitch-free selection during address setup/hold windows, preventing spurious peripheral access.

Bus Multiplexing

Logic State Machine Control

Use Scenario: Routing data between multiple sensors and a single ADC channel in a PLC analog input module.

IC Role / Device Role / Timing Role: SN74LS138NSR functions as an 8:1 demultiplexer, steering sensor outputs based on controller address bits.

Use Value: Enables time-division sampling of eight channels with no external switching transistors or timing overhead.

Use Scenario: Generating state-specific control signals (e.g., reset, load, shift) in a 3-bit finite-state machine for motor sequencing.

IC Role / Device Role / Timing Role: SN74LS138NSR converts current state register output into discrete active-low control lines.

Use Value: Replaces complex PAL programming with fixed, predictable, and radiation-tolerant TTL logic for safety-critical sequences.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-to-8 decoder applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LS138N	Same logic function and electrical specs, but in 16-pin PDIP package with through-hole mounting.	Preferred for prototyping, repair, or legacy through-hole PCBs where reworkability is critical.	Select SN74LS138N when manual soldering or socket-based testing is required; SN74LS138NSR is optimal for automated SMT production.
SN74HC138DR	CMOS version with wider V_CC range (2 V–6 V), lower I_CC, but higher propagation delay (23 ns typ at 4.5 V) and different input thresholds.	Suitable for battery-powered or mixed-voltage systems where power efficiency outweighs strict TTL compatibility.	Choose SN74HC138DR only if supply voltage flexibility or static power reduction is prioritized over guaranteed LS-TTL interoperability.

Compared with SN74LS138N, SN74LS138NSR offers identical timing and drive strength in a space-saving SOP package ideal for volume manufacturing; versus SN74HC138DR, it guarantees LS-TTL voltage compatibility and faster edge response in legacy 5 V systems.

Availability

SN74LS138NSR is available at Aetrix Electronics and suitable for industrial control panels, legacy microprocessor upgrades, and test equipment requiring stable component supply with long-term obsolescence management.

Supply support for SN74LS138NSR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial and automotive qualification.

The SN74LS138NSR belongs to TI's legacy 74LS logic family, designed specifically for reliable, low-cost address decoding and signal routing in commercial-grade digital systems from the 1970s onward.

FAQ

What is the maximum operating frequency supported by the SN74LS138NSR?

The SN74LS138NSR does not specify a maximum clock frequency because it is a combinational logic device without internal clocking. Its usable speed is determined by propagation delay: 22 ns maximum from input to output ensures reliable operation in systems with address setup/hold times ≥25 ns, such as 8085 or Z80-based designs running below 20 MHz.

Can the SN74LS138NSR be used in place of the SN74LS138N on the same PCB?

No - the SN74LS138NSR uses a 16-pin SOP (NS) footprint with 1.27 mm pitch, while the SN74LS138N uses a 16-pin PDIP (N) package with 0.3 inch row spacing. Their land patterns and soldering methods are incompatible; redesigning the PCB layout is required to substitute SN74LS138NSR for SN74LS138N.

Does the SN74LS138NSR support mixed-voltage interfacing with 3.3 V logic?

The SN74LS138NSR is specified only for 5 V operation (4.75–5.25 V). Its input high threshold (V_IH ≥ 2.0 V) may accept 3.3 V logic highs marginally, but output high voltage (V_OH ≥ 2.7 V at I_OH = –0.4 mA) falls below typical 3.3 V CMOS input requirements. Direct interfacing is not recommended without level-shifting circuitry for the SN74LS138NSR.

How are the enable inputs configured for basic operation of the SN74LS138NSR?

For standard 3-to-8 decoding, tie G1 to V_CC (high), and connect both G2A and G2B to ground (low). This activates the decoder so that outputs Y0–Y7 respond to address inputs A, B, and C. Any deviation - e.g., G1 low or either G2 input high - forces all outputs high, disabling selection.

Is the SN74LS138NSR RoHS compliant and lead-free?

Yes - the SN74LS138NSR uses NiPdAu (NIPDAU) lead finish and is RoHS compliant (per TI documentation), with Level-1 moisture sensitivity rating and peak reflow tolerance up to 260 °C. It contains no lead in its terminations and meets EU Directive 2011/65/EU requirements for hazardous substances.

SN74LS138NSR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74LS

Package/Case:: 16-SOIC (0.209", 5.30mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Type:: Decoder/Demultiplexer

Circuit:: 1 x 3:8

Independent Circuits:: 1

Current - Output High, Low:: 400µA, 8mA

Voltage Supply Source:: Single Supply

Voltage - Supply:: 4.75V ~ 5.25V

Operating Temperature:: 0°C ~ 70°C

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SO

SN74LS138NSR FAQ

1.How can I place an order for SN74LS138NSR through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74LS138NSR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74LS138NSR reliable?

The price and inventory of SN74LS138NSR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS138NSR is usually 5 days.

3.What payment methods are accepted for SN74LS138NSR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS138NSR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74LS138NSR?

SN74LS138NSR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74LS138NSR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74LS138NSR?

For technical support, including SN74LS138NSR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS138NSR requirements.

6.How does Aetrix verify that SN74LS138NSR is sourced from the original manufacturer or authorized distributors?

All SN74LS138NSR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS138NSR meets industry standards.

7.What is the process for return or replacement of SN74LS138NSR?

All SN74LS138NSR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS138NSR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74LS138NSR part is unused and in its original packaging.

Return procedure for SN74LS138NSR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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