Texas Instruments SN74LS173ADR

Overview

SN74LS173ADR from Texas Instruments is a 4-bit D-type register with 3-state outputs, designed for bus-oriented TTL systems. It features independent clock and gated data-enable (G1/G2) and output-control (M/N) inputs, 18 ns typical propagation delay, 50 MHz maximum clock frequency, and operates from 4.75 V to 5.25 V at 0°C to 70°C. It serves as a bus buffer register in data path control applications.

For engineers reviewing the SN74LS173ADR datasheet, SN74LS173ADR pinout, SN74LS173ADR application, or SN74LS173ADR equivalent, key selection considerations include its 3-state output drive capability (±24 mA), low ICC (19–24 mA), dual enable architecture for precise data gating, and SOIC-16 package compatibility with high-density PCB layouts.

Technical Context

The SN74LS173ADR implements four edge-triggered D-type flip-flops with fully independent clock input and separate asynchronous clear (CLR). Its dual data-enable inputs (G1, G2) must both be low to load data on the next positive clock edge, enabling robust parallel-load control without race conditions.

Output control uses two active-low signals (M, N): either high disables all four Q outputs to high-impedance state independently of clock activity, while both low enables normal logic-level drive. This architecture supports dynamic bus sharing across up to 128 outputs per bus line under TTL load rules.

Key Specifications

Pinout & Package

SN74LS173ADR is supplied in a 16-pin SOIC (D) package with 1.27 mm pitch, 7.5 mm body width, and RoHS-compliant NiPdAu lead finish. It complies with JEDEC MS-012, has moisture sensitivity level 1, and supports standard reflow profiles up to 260°C peak.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar 4-bit D-type register with 3-state output applications.

Compared with SN74LS174ADR and SN74LS373N, the SN74LS173ADR uniquely combines edge-triggered 4-bit storage, dual-gated data load, and dual-independent 3-state control - making it the only option among the three for synchronous, contention-free bus interfacing with minimal external logic.

Availability

SN74LS173ADR is available at Aetrix Electronics and suitable for industrial PLC I/O expansion, legacy bus interface adapters, test equipment pattern generators, and embedded system configuration latches requiring stable component supply and long-term obsolescence management.

Supply support for SN74LS173ADR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader founded in 1930, specializing in analog, embedded processing, and logic devices with broad industrial, automotive, and communications portfolio coverage.

The SN74LS173ADR belongs to TI's legacy 74LS logic family, engineered specifically for robust, low-power, TTL-compatible bus interfacing in cost-sensitive and reliability-critical industrial control systems.

FAQ

What is the maximum clock frequency supported by the SN74LS173ADR?

The SN74LS173ADR supports a maximum clock frequency of 50 MHz under recommended operating conditions (VCC = 5 V, TA = 25°C, CL = 45 pF). This value is confirmed in the switching characteristics table for SN74LS173A, and applies directly to the SN74LS173ADR variant in SOIC-D package. At higher temperatures or capacitive loads, derating is required per timing specifications.

How do the M and N pins function on the SN74LS173ADR?

The M and N pins on the SN74LS173ADR are active-low output control terminals. When both are low, the four Q outputs drive normal logic levels. If either M or N is high, all Q outputs enter high-impedance state - independent of clock, clear, or data inputs. This dual-input design provides redundancy and flexible bus arbitration control in the SN74LS173ADR.

Does the SN74LS173ADR have an asynchronous clear function?

Yes, the SN74LS173ADR includes an active-high asynchronous clear (CLR) input on pin 10. When asserted, CLR forces all four Q outputs low immediately - overriding clock edges, data-enable states, and output-control settings. This function is fully documented in the function table and timing diagrams of the SN74LS173ADR datasheet.

What is the supply current consumption of the SN74LS173ADR?

The SN74LS173ADR draws 19 mA typical and 24 mA maximum supply current (ICC) under recommended operating conditions (VCC = 5.25 V, all outputs open, CLR grounded, G1/G2/N/M at 4.5 V). This represents a significant reduction versus the original SN74173 (50–72 mA), confirming its low-power Schottky design advantage in the SN74LS173ADR.

Is the SN74LS173ADR pin-compatible with through-hole versions like SN74LS173AN?

Yes, the SN74LS173ADR is pin-compatible with SN74LS173AN (PDIP-16) and SN74LS173AJ (CDIP-16). All share identical pin numbering, signal definitions, and electrical behavior per the SDLS067A datasheet. The only differences are package type (SOIC vs. DIP), thermal resistance (113°C/W vs. 78°C/W), and reflow compatibility - making SN74LS173ADR a direct surface-mount upgrade path.