Texas Instruments SN74LS221DR
- Part No.:
- SN74LS221DR
- Manufacturer:
- Texas Instruments
- Category:
- Multivibrators
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74LS221DR.pdf
- Description:
- IC MULTIVIBRATOR 45NS 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:4,057
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74LS221DR from Texas Instruments is a dual TTL monostable multivibrator with independent negative- and positive-transition-triggered inputs per channel, 70 ns maximum output pulse length at VCC = 5 V, Schmitt-trigger B-input for jitter-free triggering down to 1 V/s, and overriding clear functionality. It serves as a precision timing element in digital logic systems requiring stable, retriggerable one-shot pulses - e.g., debouncing mechanical switches or generating fixed-width strobes in legacy industrial controllers.
For engineers reviewing the SN74LS221DR datasheet, SN74LS221DR pinout, SN74LS221DR application, or SN74LS221DR equivalent, key selection considerations include its 16-pin SOIC-D package, LS-family TTL compatibility (IOL = 8 mA, IOH = −400 µA), external Rext/Cext-determined pulse width (0.7·RextCext), ±0.5% unit-to-unit pulse width variation, and operating range of 0°C to 70°C.
Technical Context
The SN74LS221DR implements two independent monostable multivibrators sharing no internal coupling; each features dual trigger inputs (A: positive-edge sensitive, B: Schmitt-trigger negative-edge sensitive) and an overriding active-low CLR input that terminates the output pulse regardless of ongoing input transitions. Its internal latching circuitry provides high immunity to VCC noise (1.5 V typical) and ensures output stability independent of input transition rate.
Pulse width is defined solely by external Rext and Cext components via tw ≈ 0.7·RextCext, with supported ranges of 1.4 kΩ–100 kΩ for Rext and 0–1000 µF for Cext. Output rise/fall times are TTL-compatible and pulse-length-independent, while propagation delays (tPLH/tPHL) range from 20 ns to 70 ns depending on trigger source and load conditions.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | LS-TTL: compatible with standard TTL voltage thresholds and drive strength, enabling drop-in replacement in legacy 74-series designs. |
| Max Output Pulse Width | 70 ns (at Rext = 2 kΩ, Cext = 0); extends up to milliseconds with larger R/C values - supports both nanosecond reset pulses and long-duration timing intervals. |
| Input Trigger Sensitivity | B input has Schmitt-trigger hysteresis (VT+ = 1–2 V, VT− = 0.7–0.9 V), enabling reliable edge detection on slow-rising signals as low as 1 V/s - critical for noisy switch interfaces. |
| Output Drive Capability | IOL = 8 mA / IOH = −400 µA: sufficient to directly drive multiple TTL inputs or small LEDs without buffering. |
| Timing Accuracy | ±0.5% unit-to-unit pulse width variation at fixed Rext/Cext; pulse stability virtually independent of VCC and temperature - reduces calibration burden in production test. |
| Operating Temperature | 0°C to 70°C: qualified for commercial-grade embedded systems, not rated for extended industrial or automotive environments. |
Pinout & Package
SN74LS221DR is housed in a 16-pin SOIC (D) package with 1.27 mm pitch, 7.5 mm width, and tape-and-reel packaging (2500 units/reel). Pin assignments match SN54/74123 and SN54/74LS123 devices, enabling direct substitution where retriggering is not required.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 2, 3, 4, 5, 6, 13, 14, 15, 16 | Input/Output Terminals (1A, 1B, 1CLR, 1Q, 1Q̅, 2A, 2B, 2CLR, 2Q, 2Q̅) | Dual independent monostable channels: each has A (positive-edge), B (Schmitt negative-edge), CLR (active-low override), Q/Q̅ outputs. |
| 7 | GND | Ground reference for all logic and timing circuits; must be low-impedance for stable pulse width. |
| 8 | VCC | +5 V supply; decoupling capacitor (0.1 µF) required near pin for noise immunity during output transitions. |
| 9, 10, 11, 12 | Timing Terminals (1Rext/Cext, 1Cext, 2Rext/Cext, 2Cext) | External RC network connections: Rext/Cext node ties to internal timing comparator; Cext connects to ground - polarity matters for correct operation. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent monostables | Enables two separate timing functions on one IC - reduces board space and component count vs. discrete 555-based solutions. |
| Overriding clear input | Active-low CLR forces immediate Q low regardless of ongoing A/B transitions - essential for fail-safe pulse termination in safety-critical logic. |
| Jitter-free Schmitt B-input | Eliminates false triggering from slow or noisy edges (down to 1 V/s), removing need for external RC filtering in switch debounce applications. |
| Wide Rext/Cext range | Supports timing from 35 ns (R=2 kΩ, C=0) to >7 ms (R=10 kΩ, C=1 µF) - covers reset, strobe, delay, and oscillator use cases with one device family. |
| LS-TTL compatibility | Matches input thresholds and output drive of standard 74LS logic - integrates seamlessly into existing TTL bus structures without level-shifting. |
Applications
| Switch Debounce | Hardware Reset Generation |
|---|---|
Use Scenario: Mechanical pushbutton connected to microcontroller GPIO with contact bounce causing multiple interrupts. IC Role / Device Role / Timing Role: Monostable multivibrator triggered by button closure (B input), generating clean single-pulse output to synchronize with clock domain. Use Value: Eliminates software debounce overhead; 70 ns minimum pulse width ensures reliable capture by 10 MHz+ logic; Schmitt input rejects EMI-induced glitches. | Use Scenario: Power-on reset circuit for FPGA or microprocessor requiring precise 100–500 ns active-low reset pulse after VCC stabilization. IC Role / Device Role / Timing Role: One-shot configured with Rext=2 kΩ, Cext=0 to produce 30 ns–70 ns TTL-compatible reset pulse upon power-up trigger. Use Value: Guarantees deterministic reset width independent of supply ramp rate; LS drive strength meets FPGA reset pin IIL requirements without pull-up resistor. |
| Pulse Width Modulation Interface | Digital Timing Reference Generator |
Use Scenario: Legacy industrial PLC using analog PWM signal to control motor speed, requiring conversion to fixed-frequency digital enable pulses. IC Role / Device Role / Timing Role: B input triggered by PWM falling edge; Q output drives optocoupler with duty-cycle-independent pulse width set by Rext/Cext. Use Value: Converts variable-duty analog signal to stable digital timing; ±0.5% pulse width consistency ensures repeatable motor torque response across units. | Use Scenario: Test equipment needing precise, jitter-free strobe signals synchronized to external clock for sampling ADCs or capturing serial data. IC Role / Device Role / Timing Role: Dual-channel configuration: Channel 1 generates master strobe; Channel 2 provides delayed strobe using separate Rext/Cext network. Use Value: Enables sub-microsecond inter-pulse timing control; identical propagation delays between channels ensure phase coherence in multi-channel acquisition systems. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar monostable multivibrator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS123DR | Retriggerable architecture; different internal timing path yields shorter min pulse width (25 ns) but higher ICC (27 mA vs. 11 mA quiescent). | Preferred when input pulses may occur before prior output completes; unsuitable if strict non-retriggerable behavior is required. | Select SN74LS123DR only when retriggering is explicitly needed; SN74LS221DR is superior for fixed-duration, non-overlapping pulses. |
| CD74HC221M | High-speed CMOS: wider VCC range (2–6 V), lower ICC (4 µA), but no Schmitt B-input and reduced noise immunity (no 1.5 V VCC noise margin). | Suitable for battery-powered or mixed-voltage systems; requires external hysteresis for noisy inputs, increasing BOM count. | Choose CD74HC221M for low-power or wide-supply designs; retain SN74LS221DR for noise-prone industrial environments with fixed 5 V rails. |
Compared with SN74LS123DR and CD74HC221M, the SN74LS221DR uniquely balances LS-TTL compatibility, built-in Schmitt noise immunity, and non-retriggerable precision timing - making it optimal for legacy 5 V systems where signal integrity and deterministic pulse behavior are prioritized over power savings or retriggering flexibility.
Availability
SN74LS221DR is available at Aetrix Electronics and suitable for industrial control panels, legacy instrumentation, and repair of vintage computing hardware requiring stable component supply with full traceability and long-term lifecycle support.
Supply support for SN74LS221DR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog and embedded processing technologies with broad portfolio coverage across industrial, automotive, and communications markets.
The SN74LS221DR belongs to TI's legacy 74LS logic family, designed specifically for robust, pin-compatible upgrades of earlier 74121/74123 monostables in commercial-grade digital systems requiring predictable timing and TTL interoperability.
FAQ
What is the maximum recommended external timing resistance for SN74LS221DR?
The maximum recommended external timing resistance (Rext) for SN74LS221DR is 100 kΩ. This value ensures jitter-free operation across the full 0°C to 70°C temperature range and 4.75 V to 5.25 V supply voltage window. Using Rext > 100 kΩ may increase susceptibility to noise-induced timing variation, especially at temperature extremes. The SN74LS221DR datasheet specifies this limit based on empirical characterization of pulse width stability and propagation delay consistency.
Can SN74LS221DR generate pulses shorter than 70 ns?
Yes, SN74LS221DR can generate pulses significantly shorter than 70 ns. With Rext = 2 kΩ and Cext = 0, the typical output pulse width is 30 ns and minimum is 20 ns - verified under VCC = 5 V, TA = 25°C, and RL = 2 kΩ load conditions. This capability makes SN74LS221DR suitable for generating precise reset or strobe signals in high-speed digital logic where sub-50 ns timing is required.
Does SN74LS221DR support retriggering during an active output pulse?
No, SN74LS221DR does not support retriggering. Once triggered, the output pulse duration is determined solely by the external Rext/Cext network and cannot be extended or restarted by subsequent A or B input transitions. This non-retriggerable behavior distinguishes it from the SN74LS123 and ensures deterministic, fixed-width timing - critical in applications like hardware reset generation where overlapping pulses must be avoided.
What is the purpose of the NC pins on SN74LS221DR?
SN74LS221DR has four NC (No Connection) pins: pins 3, 4, 5, and 6 in the 16-pin SOIC-D package. These pins have no internal connection and must remain unconnected in the PCB layout. They exist due to shared die design with other members of the '221 family (e.g., SN54221J with different pinout) and do not affect electrical performance. Leaving them floating is acceptable; tying them to GND or VCC is unnecessary and not recommended.
How does the Schmitt-trigger input on SN74LS221DR improve noise immunity?
The Schmitt-trigger input on the B terminal of SN74LS221DR provides hysteresis with VT+ ≈ 1–2 V and VT− ≈ 0.7–0.9 V, giving a noise margin of ~1.2 V. This allows reliable triggering from slowly rising or noisy signals (as slow as 1 V/s) without false edges - unlike standard TTL inputs. In practice, this eliminates need for external RC filters in switch debounce or sensor interface applications, reducing component count and improving system reliability in electrically harsh environments.
SN74LS221DR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LS
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Monostable
- Independent Circuits:
- 2
- Schmitt Trigger Input:
- No
- Propagation Delay:
- 45 ns
- Current - Output High, Low:
- 400µA, 8mA
- Voltage - Supply:
- 4.75 V ~ 5.25 V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SN74LS221DR FAQ
1.How can I place an order for SN74LS221DR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS221DR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS221DR reliable?
The price and inventory of SN74LS221DR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS221DR is usually 5 days.
3.What payment methods are accepted for SN74LS221DR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS221DR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LS221DR?
SN74LS221DR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS221DR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS221DR?
For technical support, including SN74LS221DR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS221DR requirements.
6.How does Aetrix verify that SN74LS221DR is sourced from the original manufacturer or authorized distributors?
All SN74LS221DR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS221DR meets industry standards.
7.What is the process for return or replacement of SN74LS221DR?
All SN74LS221DR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS221DR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS221DR part is unused and in its original packaging.
Return procedure for SN74LS221DR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74LS221DR Tags

-
SN74LVC1G123DCUR
Texas Instruments
-
CD4047BM96
Texas Instruments

-
SN74LVC1G123DCTR
Texas Instruments
-
CD74HC221M96
Texas Instruments

-
CD14538BE
Texas Instruments

-
SN74LVC1G123YZPR
Texas Instruments

-
SN74LVC1G123DCUT
Texas Instruments
-
MC14538BDR2G
onsemi

-
74VHC123AMX
onsemi

-
LTC6993CS6-2#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-3#TRMPBF
Analog Devices Inc.

-
LTC6993CS6-1#TRMPBF
Analog Devices Inc.
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
