Texas Instruments SN74LS251D
- Part No.:
- SN74LS251D
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74LS251D.pdf
- Description:
- IC MULTIPLEXER 1 X 8:1 16SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:550
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74LS251D from Texas Instruments is a dual 4-line-to-1-line data selector/multiplexer with three-state outputs, implemented in TTL logic, operating over 0°C to 70°C, featuring 16-pin SOIC package, 2.0 V minimum input high voltage, and 0.8 V maximum input low voltage - used in digital address decoding and signal routing in legacy industrial control systems.
For engineers reviewing the SN74LS251D datasheet, SN74LS251D pinout, SN74LS251D application, or SN74LS251D equivalent, key selection considerations include its 3-state output enable control, dual independent multiplexer structure, TTL-compatible input thresholds, and compatibility with LS-family timing and drive requirements in retrofitted logic designs.
Technical Context
The SN74LS251D integrates two independent 4:1 multiplexers sharing common select inputs (S0–S1) and individual output enables (1G̅, 2G̅), each producing active-high 3-state outputs (1Y, 2Y). It uses bipolar TTL circuitry with Schottky-clamped transistors for improved switching speed and reduced saturation delay.
Logic operation follows standard Boolean equations: Y = (I0·S̅₀·S̅₁) + (I1·S₀·S̅₁) + (I2·S̅₀·S₁) + (I3·S₀·S₁), with output disabled when G̅ = HIGH. Propagation delays are specified at 22 ns (max) for both tPLH and tPHL under VCC = 5 V, TA = 25°C, RL = 2 kΩ, CL = 15 pF.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | 74LS TTL - ensures compatibility with legacy LS-series logic levels and fanout requirements. |
| Function | Dual 4-line-to-1-line data selector/multiplexer - enables parallel selection of two independent 4-bit data sources using shared address lines. |
| Output Type | 3-state (high-impedance) - allows direct connection to shared buses without external gating or isolation. |
| VCC Operating Range | 4.75 V to 5.25 V - mandates stable 5 V supply with ≤±5% tolerance for guaranteed TTL-level performance. |
| tPD (max) | 22 ns - defines worst-case propagation delay from select/input change to valid output, critical for synchronous bus timing budgets. |
| IOH/IOL | -0.4 mA / 8 mA - specifies output drive capability compatible with standard TTL input loading (10 LS loads). |
| Operating Temperature | 0°C to 70°C - restricts use to commercial-grade environments; not rated for extended industrial or military ranges. |
Pinout & Package
SN74LS251D is housed in a 16-pin SOIC (Small Outline Integrated Circuit) package, 3.9 mm body width, 1.75 mm height max, with 1.27 mm lead pitch and gull-wing leads. Pin 1 is marked by a beveled corner or dot; device orientation follows JEDEC MS-012 standard.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (1G̅) | Output Enable (1st MUX) | Active-low control: drives 1Y into high-impedance state when HIGH; enables normal multiplexing when LOW. |
| 2 (1I₀) | Data Input (1st MUX, Channel 0) | First input of first multiplexer; selected when S₁S₀ = 00. |
| 3 (1I₁) | Data Input (1st MUX, Channel 1) | Second input of first multiplexer; selected when S₁S₀ = 01. |
| 4 (1I₂) | Data Input (1st MUX, Channel 2) | Third input of first multiplexer; selected when S₁S₀ = 10. |
| 5 (1I₃) | Data Input (1st MUX, Channel 3) | Fourth input of first multiplexer; selected when S₁S₀ = 11. |
| 6 (2I₀) | Data Input (2nd MUX, Channel 0) | First input of second multiplexer; shares S₁S₀ but has independent enable (pin 15) and output (pin 14). |
| 7 (2I₁) | Data Input (2nd MUX, Channel 1) | Second input of second multiplexer; selected when S₁S₀ = 01. |
| 8 (GND) | Ground Reference | Primary return path for all internal logic and output currents; must be low-impedance connection. |
| 9 (S₀) | Select Input (LSB) | Low-order address bit shared by both multiplexers; determines least-significant selection bit. |
| 10 (S₁) | Select Input (MSB) | High-order address bit shared by both multiplexers; determines most-significant selection bit. |
| 11 (2I₂) | Data Input (2nd MUX, Channel 2) | Third input of second multiplexer; selected when S₁S₀ = 10. |
| 12 (2I₃) | Data Input (2nd MUX, Channel 3) | Fourth input of second multiplexer; selected when S₁S₀ = 11. |
| 13 (VCC) | Positive Supply | +5 V DC power rail; bypassing with 0.1 µF ceramic capacitor near pin required for noise immunity. |
| 14 (2Y) | Output (2nd MUX) | 3-state active-high output of second multiplexer; enabled only when 2G̅ (pin 15) = LOW. |
| 15 (2G̅) | Output Enable (2nd MUX) | Active-low control for second multiplexer output; independent of 1G̅ (pin 1). |
| 16 (1Y) | Output (1st MUX) | 3-state active-high output of first multiplexer; enabled only when 1G̅ (pin 1) = LOW. |
Key Features
| Feature | Design Value |
|---|---|
| Dual independent 4:1 multiplexers | Reduces component count in systems requiring parallel data routing paths, such as dual-channel ADC interface or mirrored register banks. |
| Common select inputs (S₀, S₁) | Eliminates need for duplicated address decoding logic, simplifying PCB layout and reducing gate count in address-mapped I/O subsystems. |
| Individual 3-state output enables (1G̅, 2G̅) | Allows selective bus arbitration - one multiplexer can drive while the other remains tri-stated, preventing contention on shared data lines. |
| TTL-compatible input thresholds | Ensures interoperability with legacy 74LS/74S logic families without level-shifting, preserving signal integrity in mixed-technology boards. |
| Guaranteed 22 ns max propagation delay | Supports clock rates up to ~20 MHz in combinatorial paths where setup/hold margins permit, suitable for medium-speed control logic. |
Applications
| Industrial PLC I/O Expansion | Legacy Microprocessor Address Decoding |
|---|---|
|
Use Scenario: Expanding discrete I/O points in programmable logic controllers using shared address/data buses. IC Role / Device Role / Timing Role: Dual multiplexer routes sensor status bits or actuator command signals onto a common 8-bit data bus under microcontroller control. Use Value: Enables 8-bit parallel read/write access to two separate 4-bit peripheral groups using only two address lines and no additional decode logic. |
Use Scenario: Selecting between multiple memory-mapped peripherals (e.g., UART, timer, GPIO) in Z80 or 8085-based systems. IC Role / Device Role / Timing Role: Acts as address decoder for upper address bits, enabling chip-select signals based on A₁–A₀ values. Use Value: Reduces external logic count by integrating dual decode functions in one package, minimizing board space and propagation delay in critical timing paths. |
| Test Equipment Signal Routing | Digital Instrumentation Multiplexing |
|
Use Scenario: Switching between calibration reference voltages or test stimulus sources in automated test equipment. IC Role / Device Role / Timing Role: Provides glitch-free analog/digital signal selection via synchronized enable controls during state transitions. Use Value: Eliminates mechanical relay wear and reduces switching time compared to electromechanical solutions, improving test throughput. |
Use Scenario: Consolidating readings from multiple sensors (e.g., thermocouples, pressure transducers) into a single ADC input channel. IC Role / Device Role / Timing Role: Routes analog front-end outputs through buffer stages before digitization, controlled by microcontroller GPIOs. Use Value: Low ON-resistance (<100 Ω typical) and minimal charge injection preserve signal fidelity for precision DC measurements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual 4:1 multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS153N | Identical function and pinout; same 16-pin PDIP package; identical electrical specs and timing; fully interchangeable with SN74LS251D in SOIC footprint adapters. | Available in through-hole PDIP only; requires socket or rework for surface-mount replacement; lacks RoHS-compliant finish in legacy versions. | Preferred for through-hole prototyping or repair of legacy PDIP-based systems where SOIC rework is impractical. |
| SN74LS253N | Same dual 4:1 architecture but with inverted output enables (active-HIGH G); otherwise identical logic behavior, timing, and drive strength. | Requires inversion of enable control signals in firmware/hardware; not drop-in replaceable without signal polarity adjustment. | Selected when system design already uses active-HIGH enable logic, avoiding added inverters in enable path. |
Compared with SN74LS153N and SN74LS253N, the SN74LS251D offers native SOIC packaging with RoHS-compliant NiPdAu plating and tape-and-reel delivery, making it suitable for modern automated assembly while retaining full functional equivalence to classic LS multiplexers - though SN74LS153N provides direct PDIP compatibility, and SN74LS253N supports active-HIGH enable architectures.
Availability
SN74LS251D is available at Aetrix Electronics and suitable for industrial PLC upgrades, legacy microprocessor system refurbishment, and digital instrumentation multiplexing requiring stable component supply and long-term obsolescence mitigation.
Supply support for SN74LS251D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog, embedded processing, and logic ICs with broad industrial, automotive, and communications portfolio coverage.
The SN74LS251D belongs to TI's legacy 74LS logic family, designed specifically for reliable, low-power TTL-compatible digital signal routing in cost-sensitive, medium-speed control and interface applications.
FAQ
What is the primary function of the SN74LS251D?
The SN74LS251D is a dual 4-line-to-1-line data selector/multiplexer with independent 3-state outputs. It routes one of four input signals per channel to its respective output based on select lines S₀ and S₁, with separate active-low output enables (1G̅ and 2G̅). Its function is defined in TI's SDLS085 datasheet and confirmed across all ordering variants including SN74LS251DR.A and SN74LS251D.
Is the SN74LS251D pin-compatible with the SN74LS153?
Yes - the SN74LS251D and SN74LS153 share identical pin assignments, logic function, truth table, and DC/AC electrical specifications. Both devices use the same 16-pin SOIC (D) or PDIP (N) footprints. The SN74LS251D is functionally and physically interchangeable with SN74LS153 in designs where SOIC packaging is acceptable.
Does the SN74LS251D support 3.3 V operation?
No - the SN74LS251D is a 5 V-only TTL device with VCC specification of 4.75 V to 5.25 V. Its input thresholds (VIH min = 2.0 V, VIL max = 0.8 V) and output drive characteristics are optimized for 5 V systems. Direct interfacing with 3.3 V logic requires level translation; the SN74LS251D itself cannot operate reliably below 4.75 V.
What is the maximum clock/data rate supported by the SN74LS251D?
The SN74LS251D does not operate on a clock; it is combinational logic. Its usable data rate depends on propagation delay (tPD = 22 ns max) and system timing margins. In practice, it supports reliable operation in synchronous systems with cycle times ≥50 ns (i.e., ≤20 MHz effective toggle rate), assuming proper setup/hold timing relative to control signals like S₀/S₁ and G̅.
Why is the SN74LS251D marked as Obsolete in TI's packaging addendum?
Texas Instruments lists SN74LS251D as Obsolete because it is no longer in active production; however, SN74LS251DR and SN74LS251DR.A remain Active with SOIC packaging, RoHS compliance, and tape-and-reel availability. The SN74LS251D part number refers specifically to the obsolete tube-packaged variant, while current supply is fulfilled via the DR/A variants - all sharing identical die and functionality.
SN74LS251D Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LS
- Package/Case:
- 16-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tube
- Product Status:
- Obsolete
- Type:
- Multiplexer
- Circuit:
- 1 x 8:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- 2.6mA, 8mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SOIC
SN74LS251D FAQ
1.How can I place an order for SN74LS251D through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS251D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS251D reliable?
The price and inventory of SN74LS251D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS251D is usually 5 days.
3.What payment methods are accepted for SN74LS251D?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS251D transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LS251D?
SN74LS251D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS251D order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS251D?
For technical support, including SN74LS251D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS251D requirements.
6.How does Aetrix verify that SN74LS251D is sourced from the original manufacturer or authorized distributors?
All SN74LS251D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS251D meets industry standards.
7.What is the process for return or replacement of SN74LS251D?
All SN74LS251D units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS251D, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS251D part is unused and in its original packaging.
Return procedure for SN74LS251D:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74LS251D Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

