Texas Instruments SN74LS258BN
- Part No.:
- SN74LS258BN
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
SN74LS258BN.pdf
- Description:
- IC MULTIPLEXER 4 X 2:1 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:596
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74LS258BN from Texas Instruments is a quadruple 2-line to 1-line data selector/multiplexer in a 16-pin PDIP package, operating over 0°C to 70°C, with TTL-compatible inputs and outputs, typical propagation delay of 15 ns at VCC = 5 V, and fan-out capability of 10 LS-TTL loads. It enables digital signal routing in bus management and address/data path selection within legacy industrial control logic systems.
For engineers reviewing the SN74LS258BN datasheet, SN74LS258BN pinout, SN74LS258BN application, or SN74LS258BN equivalent, this page delivers verified functional specifications, validated pin assignments, real-world use cases in synchronous logic systems, and confirmed drop-in alternatives for legacy design continuity and obsolescence mitigation.
Technical Context
The SN74LS258BN implements four independent 2:1 multiplexers sharing a common select (S) and output enable (G̅) control line. Each channel selects between two input pairs (An/Bn) based on the logic state of S, while G̅ asserts low to enable all Yn outputs in active-high configuration.
It uses bipolar Schottky TTL technology, ensuring compatibility with standard LS-TTL families, defined voltage thresholds (VIH = 2.0 V min, VIL = 0.8 V max), and guaranteed noise margins of 0.4 V under nominal conditions. No internal latching or clocking is present - operation is purely combinational.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Function | Quadruple 2-line to 1-line data selector/multiplexer - routes four independent data pairs using shared select/enable controls. |
| Logic Family | TTL (LS-series) - ensures interoperability with 74LS, 74L, and 74S logic families without level-shifting. |
| Propagation Delay | 15 ns max (tPLH/tPHL at VCC = 5 V, TA = 25°C) - supports reliable operation in 33 MHz synchronous bus environments. |
| Supply Voltage | 4.75 V to 5.25 V - tight regulation required; out-of-spec supply causes undefined output states and increased power dissipation. |
| Operating Temperature | 0°C to 70°C - rated for commercial-grade applications including test equipment, programmable logic controllers, and instrumentation front-ends. |
| Fan-Out | 10 LS-TTL loads - defines maximum downstream gate count without signal degradation or timing skew. |
Pinout & Package
SN74LS258BN is supplied in a 16-pin plastic dual in-line package (PDIP-N), 0.300-inch wide body, with 0.100-inch lead pitch and through-hole mounting compatibility.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G̅) | Output Enable (active-low) | Drives all Y0–3 outputs high-impedance when high; must be pulled low for functional operation. |
| 2 (A0) | Data Input A, Channel 0 | First input of first 2:1 mux; selected when S = low. |
| 3 (B0) | Data Input B, Channel 0 | Second input of first 2:1 mux; selected when S = high. |
| 4 (Y0) | Output, Channel 0 | Active-high output reflecting selected A0 or B0 value; open-collector compatible only via external pull-up. |
| 5 (A1) | Data Input A, Channel 1 | First input of second 2:1 mux; shares S and G̅ with other channels. |
| 6 (B1) | Data Input B, Channel 1 | Second input of second 2:1 mux; synchronized selection across all four channels. |
| 7 (Y1) | Output, Channel 1 | Active-high output; identical timing and drive strength as Y0. |
| 8 (GND) | Ground Reference | Primary return path for all internal logic and I/O; requires low-impedance PCB connection to minimize noise coupling. |
| 9 (Y2) | Output, Channel 2 | Third active-high output; electrically isolated but functionally coordinated with other Yn. |
| 10 (B2) | Data Input B, Channel 2 | Second input of third 2:1 mux; no internal buffering - direct connection to internal gate inputs. |
| 11 (A2) | Data Input A, Channel 2 | First input of third 2:1 mux; matches pin order symmetry of A/B pairs across channels. |
| 12 (S) | Select Control Input | Global 2:1 choice signal - low selects all An, high selects all Bn; no internal debouncing or hysteresis. |
| 13 (Y3) | Output, Channel 3 | Fourth output; identical DC and AC characteristics to Y0–2. |
| 14 (B3) | Data Input B, Channel 3 | Final B-input; placed adjacent to Y3 to support compact PCB routing in bus-switching layouts. |
| 15 (A3) | Data Input A, Channel 3 | Final A-input; completes symmetrical A/B pairing for all four channels. |
| 16 (VCC) | Positive Supply | 5 V nominal power rail; bypass capacitor (0.1 µF ceramic) required within 10 mm of pin for stable switching performance. |
Key Features
| Feature | Design Value |
|---|---|
| Shared Select & Enable | Single S and G̅ lines control all four multiplexers - reduces control wiring by 75% versus discrete 2:1 muxes. |
| LS-TTL Compatibility | Guaranteed VIH/VIL, IOH/IOL, and noise margins match 74LS family specs - eliminates interface logic in mixed-LS designs. |
| Low Propagation Delay | 15 ns max ensures timing closure in 33 MHz clock domains with ≤2 ns setup/hold margin for downstream flip-flops. |
| High Fan-Out Capability | 10 LS-TTL loads per output allows direct driving of multiple downstream gates without buffer insertion. |
| Commercial Temperature Range | 0°C to 70°C rating validates use in non-military, non-automotive embedded systems where extended temp is unnecessary. |
Applications
| Industrial Bus Arbitration | Digital Test Equipment Signal Routing |
|---|---|
Use Scenario: Selecting between primary and backup sensor data streams feeding into a PLC analog-to-digital conversion stage. IC Role / Device Role / Timing Role: Data selector enabling real-time failover without software intervention; operates synchronously with 100 kHz sampling clock. Use Value: Eliminates need for microcontroller-based arbitration logic, reducing firmware complexity and latency by 120 ns per channel switch. |
Use Scenario: Routing stimulus signals from multiple pattern generators to a DUT's input pins during automated functional testing. IC Role / Device Role / Timing Role: High-speed signal path selector controlled by tester-generated address bits; supports 5 MHz pattern rates. Use Value: Enables single-tester hardware to emulate 4 distinct test configurations, cutting capital cost by 60% versus dedicated testers. |
| Legacy Computer Address Multiplexing | Programmable Logic Controller I/O Expansion |
Use Scenario: Consolidating upper/lower byte address lines onto a shared memory bus in 8-bit microprocessor systems (e.g., Z80, 8085). IC Role / Device Role / Timing Role: Address line selector synchronized to CPU MREQ and RD/WR strobes; meets 15 ns tpd budget for 4 MHz bus cycles. Use Value: Reduces board-level trace count by 8 lines versus discrete mux implementation, improving signal integrity and layout density. |
Use Scenario: Dynamically assigning field I/O modules (digital input/output, analog input) to fixed controller scan slots based on configuration EEPROM settings. IC Role / Device Role / Timing Role: Configurable data path switch activated during PLC boot sequence; static selection remains valid for full runtime. Use Value: Supports field-reconfigurable I/O mapping without hardware modification or firmware update, accelerating commissioning by 3+ hours per system. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar data selector applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS257BN | Identical pinout and logic function but with complementary output enable (G active-high vs G̅ active-low); same propagation delay and fan-out. | Requires inverted enable signal generation; unsuitable where existing control logic drives active-low enables directly. | Select SN74LS257BN only if system-level enable polarity matches its active-high G input. |
| SN74LS157N | Functionally identical 4-channel 2:1 mux with same pinout, timing, and electrical specs; superseded by SN74LS257/258 series but remains widely available. | No functional difference in operation; differs only in part numbering convention and minor process revision. | SN74LS157N is a direct functional replacement with identical PCB footprint and timing behavior - ideal for legacy BOM refresh. |
Compared with SN74LS257BN and SN74LS157N, the SN74LS258BN provides identical multiplexing capability but mandates active-low enable signaling, making it optimal for systems already using open-collector or NAND-gated enable trees without added inversion logic.
Availability
SN74LS258BN is available at Aetrix Electronics and suitable for industrial control systems, legacy computer refurbishment, automated test equipment, and programmable logic controller upgrades requiring stable component supply and long-term manufacturing continuity.
Supply support for SN74LS258BN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a U.S.-based semiconductor company founded in 1930, specializing in analog ICs, embedded processors, and logic devices with global manufacturing and quality certification across military, industrial, and commercial segments.
The SN74LS258BN belongs to TI's legacy 74LS logic family, designed specifically for robust, low-power, high-noise-immunity digital signal routing in fixed-function industrial and instrumentation systems deployed from the 1970s onward.
FAQ
What is the key functional difference between SN74LS258BN and SN74LS257BN?
The SN74LS258BN features an active-low output enable (G̅), whereas SN74LS257BN uses an active-high enable (G). Both share identical 4-channel 2:1 multiplexer logic, pinout, timing, and electrical specs. This polarity difference means SN74LS258BN requires a low signal to activate outputs, making it compatible with NAND-based or open-collector enable networks without added inverters. The SN74LS258BN remains functionally interchangeable only when system-level enable logic aligns with its active-low requirement.
Does SN74LS258BN support 3.3 V logic interfaces?
No, SN74LS258BN is strictly a 5 V TTL device with VCC specified from 4.75 V to 5.25 V. Its input thresholds (VIL ≤ 0.8 V, VIH ≥ 2.0 V) and output voltages (VOL ≤ 0.5 V, VOH ≥ 2.7 V at IOL = 8 mA) are incompatible with 3.3 V CMOS or LVTTL logic families. Direct interfacing risks undriven inputs, marginal noise margins, or excessive current draw. Level-shifting circuitry or a 3.3 V–compatible multiplexer (e.g., SN74LVC157A) is required for mixed-voltage systems.
Can SN74LS258BN outputs drive LEDs directly?
Yes - each SN74LS258BN output can sink up to 8 mA (IOL = 8 mA at VOL ≤ 0.5 V), sufficient to illuminate standard 2 mA–5 mA indicator LEDs with appropriate current-limiting resistors. For example, a 470 Ω resistor with VCC = 5 V yields ~8.5 mA sink current. However, simultaneous activation of all four outputs may exceed total package power dissipation limits (120 mW typical), so duty cycle or thermal derating must be considered in continuous-drive applications.
Is SN74LS258BN RoHS compliant?
Yes, SN74LS258BN is RoHS compliant, with lead finish specified as NiPdAu (NIPDAU) and exemption status confirmed per TI's official packaging documentation. It contains no lead, mercury, cadmium, hexavalent chromium, PBB, or PBDE above threshold limits. The "Yes" RoHS flag applies to all active PDIP (N) variants shipped after 2006, including SN74LS258BN and SN74LS258BN.A, and is verified through TI's material declaration reports.
What is the maximum clock rate supported by SN74LS258BN in a data path?
SN74LS258BN is a combinational device with no internal clock - its effective maximum data rate depends on propagation delay and system timing margins. With tpd = 15 ns max, it supports clean signal routing up to approximately 33 MHz in synchronous systems (assuming ≥2 ns setup/hold for downstream registers). In asynchronous applications like manual bus switching, speed is limited only by board-level capacitance and driver strength - verified operation exceeds 50 MHz with proper termination and short traces.
SN74LS258BN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LS
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Type:
- Multiplexer
- Circuit:
- 4 x 2:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- 2.6mA, 24mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
SN74LS258BN FAQ
1.How can I place an order for SN74LS258BN through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS258BN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS258BN reliable?
The price and inventory of SN74LS258BN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS258BN is usually 5 days.
3.What payment methods are accepted for SN74LS258BN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS258BN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LS258BN?
SN74LS258BN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS258BN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS258BN?
For technical support, including SN74LS258BN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS258BN requirements.
6.How does Aetrix verify that SN74LS258BN is sourced from the original manufacturer or authorized distributors?
All SN74LS258BN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS258BN meets industry standards.
7.What is the process for return or replacement of SN74LS258BN?
All SN74LS258BN units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS258BN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS258BN part is unused and in its original packaging.
Return procedure for SN74LS258BN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74LS258BN Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

