onsemi SN74LS33D
- Part No.:
- SN74LS33D
- Manufacturer:
- onsemi
- Category:
- Gates and Inverters
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74LS33D.pdf
- Description:
- IC GATE NOR 4CH 2-INP 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:45,847
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Product details
Overview
SN74LS33D from Texas Instruments is a dual 2-input NAND gate with open-collector outputs, designed for wired-AND logic and level translation in TTL-compatible digital systems. It operates at VCC = 5 V, supports fan-out of 20 LS-TTL loads, features typical propagation delay of 15 ns, and is rated for industrial temperature range (−40°C to +85°C) in a 14-pin SOIC package.
For engineers reviewing the SN74LS33D datasheet, pinout, applications, or equivalent options, key selection considerations include open-collector output drive capability, TTL input compatibility, DC noise margin (0.4 V), output saturation voltage (0.4 V max at IOL = 8 mA), and absence of internal pull-up resistors requiring external termination.
Technical Context
The SN74LS33D implements two independent NAND gates with open-collector outputs, enabling direct wired-AND bus configurations without additional logic. Each gate accepts standard TTL input thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V) and delivers output low voltage ≤ 0.4 V at 8 mA sink current.
No internal pull-up is integrated; external pull-up resistors must be used to establish HIGH-level logic states. The device is fully compatible with LS-TTL family voltage and timing specifications, including guaranteed minimum high-level output voltage of 2.7 V when externally pulled up.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Supply | 5 V ±5% - fixed single-rail operation; no wide-VCC support |
| Input Logic Levels | VIH ≥ 2.0 V, VIL ≤ 0.8 V - ensures interoperability with standard TTL/LS-TTL sources |
| Output Type | Open-collector - requires external pull-up; enables wired-AND, level shifting, and bus driving |
| Propagation Delay | 15 ns typical (tpd), 25 ns max - defines maximum clock/data rate in synchronous logic paths |
| Output Sink Current | IOL = 8 mA max at VOL ≤ 0.4 V - determines minimum external pull-up resistance for target HIGH voltage |
| Operating Temperature | −40°C to +85°C - qualified for industrial environments without derating |
| Fan-Out | 20 LS-TTL loads - specifies maximum number of downstream LS inputs it can drive reliably |
Pinout & Package
SN74LS33D is housed in a 14-pin SOIC (Small Outline Integrated Circuit) package per TI drawing D, with body width 3.9 mm, lead pitch 1.27 mm, and total package dimensions 8.65 mm × 3.91 mm × 1.75 mm.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | Input A1 | First input of Gate 1; TTL-compatible voltage thresholds apply |
| 2 | Input B1 | Second input of Gate 1; tied together with A1 for inverter configuration if needed |
| 3 | Output Y1 | Open-collector output of Gate 1; requires external pull-up resistor |
| 4 | Input A2 | First input of Gate 2; electrically isolated from Gate 1 |
| 5 | Input B2 | Second input of Gate 2; supports independent logic control |
| 6 | Output Y2 | Open-collector output of Gate 2; may share pull-up with Y1 in wired-AND |
| 7 | GND | Ground reference for all inputs, outputs, and internal circuitry |
| 14 | VCC | +5 V supply rail; decoupling capacitor recommended near pin |
Key Features
| Feature | Design Value |
|---|---|
| Open-collector outputs | Enables wired-AND bus topology and interface to higher-voltage logic families (e.g., 12 V) |
| TTL-compatible inputs | Accepts standard LS-TTL logic levels without level-shifting circuitry |
| Industrial temperature range | Validated operation from −40°C to +85°C without performance degradation |
| Low power consumption | Typical ICC = 19 mA at VCC = 5 V - lower than standard TTL equivalents |
| Guaranteed switching thresholds | VIH min = 2.0 V and VIL max = 0.8 V ensure noise immunity in noisy digital environments |
Applications
| Industrial Control Bus | Legacy System Interface |
|---|---|
Use Scenario: Interfacing multiple microcontroller peripherals to a shared status interrupt line using wired-AND logic. IC Role / Device Role / Timing Role: Dual NAND gate acting as active-low interrupt combiner with open-collector outputs. Use Value: Eliminates need for discrete diodes or additional logic; supports up to 8 devices on one bus with 4.7 kΩ pull-up. | Use Scenario: Adapting 5 V TTL signals to legacy 12 V relay driver circuits. IC Role / Device Role / Timing Role: Level-translating NAND gate with open-collector output sinking into 12 V pull-up. Use Value: Provides clean logic inversion and voltage translation without external level shifters or MOSFETs. |
| Test Equipment Signal Conditioning | Digital Power Sequencing |
Use Scenario: Generating synchronized enable pulses for multiple test instrument modules based on two independent trigger conditions. IC Role / Device Role / Timing Role: Dual NAND gate implementing AND-NOT logic to gate clock or strobe signals. Use Value: Delivers sub-25 ns propagation delay and precise edge alignment across both channels. | Use Scenario: Controlling power-on sequence of three voltage rails using reset signal dependencies. IC Role / Device Role / Timing Role: NAND gate configured as inverter to invert supervisor reset and enable delayed rail activation. Use Value: Ensures deterministic startup order with TTL-compatible timing margins and robust noise rejection. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar NAND gate with open-collector output applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS03N | Same logic function and open-collector outputs; identical pinout and electrical specs; through-hole PDIP-14 package instead of SOIC. | Requires PCB layout change for through-hole assembly; same thermal and timing behavior. | Select SN74LS03N for prototyping or legacy through-hole designs where SOIC reflow is unavailable. |
| SN74ALS33AN | Advanced LS variant: faster tpLH/tpHL (10 ns typ), lower ICC (12 mA typ), but same open-collector structure and pinout. | Higher speed and lower power suit high-density logic boards; pin-compatible drop-in replacement. | Choose SN74ALS33AN when tighter timing budgets or reduced system power are required without layout change. |
Compared with SN74LS33D, SN74LS03N offers identical functionality in through-hole form for manual assembly or legacy systems, while SN74ALS33AN delivers measurable speed and power improvements with full pin and logic compatibility-enabling direct upgrade without redesign.
Availability
SN74LS33D is available at Aetrix Electronics and suitable for industrial control buses, legacy system interfaces, test equipment signal conditioning, and digital power sequencing requiring stable component supply and long-term manufacturability.
Supply support for SN74LS33D includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, specializing in analog, embedded processing, and logic solutions for industrial, automotive, and communications markets.
The SN74LS33D belongs to TI's legacy LS-TTL logic family, engineered for reliability and interoperability in fixed-function digital systems where predictable timing, noise immunity, and open-collector flexibility are essential.
FAQ
What is the output configuration of the SN74LS33D?
The SN74LS33D features two independent open-collector NAND gate outputs. Neither output includes an internal pull-up resistor, so external pull-up resistors must be used to establish HIGH logic states. This configuration allows wired-AND connections, level translation to higher voltages, and direct interfacing with other open-collector devices. The SN74LS33D output saturation voltage is specified at ≤0.4 V when sinking 8 mA.
Does the SN74LS33D support mixed-voltage interfacing?
Yes, the SN74LS33D supports mixed-voltage interfacing via its open-collector outputs. By selecting an appropriate external pull-up resistor connected to a higher supply rail (e.g., 12 V), the SN74LS33D can drive logic HIGH levels compatible with non-5 V systems. Input thresholds remain TTL-standard (VIH ≥ 2.0 V, VIL ≤ 0.8 V), ensuring reliable recognition of 5 V logic signals regardless of pull-up voltage.
What is the maximum fan-out of the SN74LS33D?
The SN74LS33D provides a fan-out of 20 LS-TTL loads per output. This rating assumes standard LS-TTL input characteristics (IIH = 20 µA, IIL = −0.4 mA) and accounts for worst-case voltage margins. Fan-out is limited by output sink current capacity (IOL = 8 mA max) and input current requirements of downstream devices. Exceeding this fan-out may degrade noise margin or increase propagation delay in the SN74LS33D.
Can the SN74LS33D be used as an inverter?
Yes, the SN74LS33D can be configured as an inverter by tying one input of either NAND gate to a constant HIGH level (e.g., VCC via pull-up). With A1 = HIGH, the output Y1 becomes the logical inverse of B1. This usage preserves the open-collector output property and maintains full compatibility with TTL logic levels. Both gates in the SN74LS33D support this configuration independently.
Is the SN74LS33D RoHS compliant?
The SN74LS33D was originally released prior to RoHS mandate and is not inherently RoHS compliant in its standard form. However, Texas Instruments offers RoHS-compliant versions under different part numbering (e.g., SN74LS33DRG4). For new designs requiring compliance, verify the suffix and packaging code against TI's official product change notices. The SN74LS33D itself remains widely used in industrial retrofits where legacy compliance rules apply.
SN74LS33D Specifications
- Product attributes
- Attribute value
- Manufacturer:
- onsemi
- Series:
- 74LS
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Logic Type:
- NOR Gate
- Number of Circuits:
- 4
- Number of Inputs:
- 2
- Features:
- Open Collector
- Voltage - Supply:
- 4.75V ~ 5.25V
- Current - Quiescent (Max):
- 3.6 mA
- Current - Output High, Low:
- -, 24mA
- Input Logic Level - Low:
- 0.8V
- Input Logic Level - High:
- 2V
- Max Propagation Delay @ V, Max CL:
- 32ns @ 5V, 45pF
- Operating Temperature:
- 0°C ~ 70°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
SN74LS33D FAQ
1.How can I place an order for SN74LS33D through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS33D on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS33D reliable?
The price and inventory of SN74LS33D are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS33D is usually 5 days.
3.What payment methods are accepted for SN74LS33D?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS33D transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LS33D?
SN74LS33D orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS33D order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS33D?
For technical support, including SN74LS33D datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS33D requirements.
6.How does Aetrix verify that SN74LS33D is sourced from the original manufacturer or authorized distributors?
All SN74LS33D products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS33D meets industry standards.
7.What is the process for return or replacement of SN74LS33D?
All SN74LS33D units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS33D, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS33D part is unused and in its original packaging.
Return procedure for SN74LS33D:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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