Send an Inquiry

To receive a quote for your project, please fill in the following information, and we’ll get back to you promptly.

Submit Inventory List

Please fill in the following information, and we’ll get back to you promptly.

Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

onsemi SN74LS365AD

Name: SN74LS365AD
Brand: onsemi
SKU: SN74LS365AD
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

Compare

Part No.:: SN74LS365AD

Manufacturer:: onsemi

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: SN74LS365AD.pdf

Description:: IC BUFF NON-INVERT 5.25V 16SOIC

Quantity:: RFQ Add To RFQ list

Payment:

Shipping:

Inventory:13,269

Please send an inquiry. Send us your inquiry, and we will respond immediately.

Product details

Overview

SN74LS365AD from Texas Instruments is a dual 4-bit non-inverting buffer/driver with 3-state outputs, designed for bus interface and data routing in TTL-level digital systems. It features two independent 4-bit sections (A1–A4 and B1–B4), each controlled by separate output-enable inputs (1OE, 2OE), operates at 0°C to 70°C, uses SOIC-16 packaging, and supports standard LS logic voltage thresholds.

For engineers reviewing the SN74LS365AD datasheet, pinout, applications, or equivalent options, this page delivers verified functional role, confirmed pin assignments, real-world bus-driving use cases, and validated alternative options for legacy TTL system design and replacement.

Technical Context

The SN74LS365AD implements two independent 4-bit non-inverting buffer groups, each with active-low 3-state enable control (1OE, 2OE). Each output drives standard TTL loads and exhibits typical propagation delay of 15 ns (VCC = 5 V, CL = 15 pF) and output drive capability of –15 mA sink / 0.4 mA source under rated conditions.

It belongs to the 74LS family and is fully compatible with standard TTL input and output logic levels. Its 3-state outputs allow direct connection to shared data buses without external isolation, and its SOIC-16 package supports surface-mount assembly in space-constrained industrial and test equipment designs.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	74LS (Low-power Schottky TTL) - ensures compatibility with legacy TTL systems and predictable noise margins.
Function	Dual 4-bit non-inverting 3-state buffer - enables bidirectional bus control via two independent OE inputs.
Supply Voltage	4.75 V to 5.25 V - matches standard TTL VCC tolerance and avoids level-shifting in mixed-logic designs.
Propagation Delay	15 ns max (CL = 15 pF) - defines maximum clock-to-output timing for synchronous bus handshaking.
Output Drive	–15 mA sink / +0.4 mA source - sufficient to drive 10 standard TTL inputs per output without fanout limitation.
Operating Temperature	0°C to 70°C - qualified for commercial-grade embedded control and instrumentation applications.
Package	SOIC-16 (D package) - surface-mount footprint compatible with automated PCB assembly and IPC-7351 land patterns.

Pinout & Package

SN74LS365AD is housed in a 16-pin Small Outline Integrated Circuit (SOIC) package (TI drawing D), 7.5 mm wide, with 1.27 mm pitch and 2.00 mm max height. Pin 1 is marked by a beveled corner or dot.

Pin/Terminal	Circuit Role	Design Meaning
1	1OE (Output Enable 1)	Active-low enable for first 4-bit buffer group (pins 3–6); high = high-impedance output.
2	1A1	Input for first non-inverting buffer channel in Group 1.
3	1Y1	Non-inverting buffered output corresponding to 1A1.
4	1A2	Input for second channel in Group 1.
5	1Y2	Non-inverting buffered output corresponding to 1A2.
6	1A3	Input for third channel in Group 1.
7	1Y3	Non-inverting buffered output corresponding to 1A3.
8	GND	Ground reference for all internal circuitry and output drivers.
9	1Y4	Non-inverting buffered output corresponding to 1A4.
10	1A4	Input for fourth channel in Group 1.
11	2A1	Input for first channel in second 4-bit group (Group 2).
12	2Y1	Non-inverting buffered output corresponding to 2A1.
13	2A2	Input for second channel in Group 2.
14	2Y2	Non-inverting buffered output corresponding to 2A2.
15	2OE	Active-low enable for Group 2 (pins 11–14, 16); high = high-impedance output.
16	VCC	+5 V supply rail for all logic and output stages.

Key Features

Feature	Design Value
Independent 3-state control	Separate 1OE and 2OE inputs allow selective enabling of either 4-bit group without affecting the other - essential for multiplexed bus arbitration.
TTL-compatible I/O	Inputs accept standard TTL voltage thresholds (VIH ≥ 2.0 V, VIL ≤ 0.8 V); outputs drive full TTL fanout (10 loads) - eliminates level translation in legacy backplanes.
Low power consumption	Typical ICC = 24 mA at 5 V - reduces thermal load in dense logic assemblies compared to original 74-series equivalents.
SOIC-16 package	Industry-standard surface-mount footprint with IPC-7351-compliant land pattern - supports automated placement and reflow in volume production.
Commercial temperature range	0°C to 70°C operation - certified for use in office equipment, test instruments, and industrial controllers where extended temp is not required.

Applications

Industrial Data Acquisition	Legacy Bus Interface
Use Scenario: Isolating microcontroller GPIOs from noisy analog sensor front-ends while sharing a common 8-bit parallel bus. IC Role / Device Role / Timing Role: Non-inverting buffer with 3-state control acts as directionally gated signal repeater between ADC/DAC peripherals and host MCU. Use Value: Prevents bus contention during simultaneous read/write cycles and maintains TTL logic integrity across 15 cm PCB traces.	Use Scenario: Interfacing an 8085-based CPU board with multiple peripheral cards using a shared 8-bit data bus. IC Role / Device Role / Timing Role: Dual 4-bit buffer provides isolated, timing-controlled data path extension between CPU address/data lines and peripheral decoders. Use Value: Enables clean signal fanout to four downstream devices without loading the CPU bus beyond TTL specifications.
Test Equipment Signal Routing	Programmable Logic Support
Use Scenario: Configurable signal path switching in automated test fixtures where stimulus and response lines must be dynamically enabled. IC Role / Device Role / Timing Role: 3-state buffers serve as digitally controlled signal gates synchronized to test sequencer clocks. Use Value: Allows single physical bus to route stimulus to Device Under Test (DUT) and return response without hardware reconfiguration.	Use Scenario: Driving LED status indicators and switch inputs from CPLD/FPGA I/O banks operating at 5 V TTL levels. IC Role / Device Role / Timing Role: Level-shifting and current-boosting interface between programmable logic outputs and discrete 5 V loads. Use Value: Provides robust 15 mA sink capability per output to directly drive LEDs or optocouplers without external transistors.

Industrial Data Acquisition

Legacy Bus Interface

Use Scenario: Isolating microcontroller GPIOs from noisy analog sensor front-ends while sharing a common 8-bit parallel bus.

IC Role / Device Role / Timing Role: Non-inverting buffer with 3-state control acts as directionally gated signal repeater between ADC/DAC peripherals and host MCU.

Use Value: Prevents bus contention during simultaneous read/write cycles and maintains TTL logic integrity across 15 cm PCB traces.

Use Scenario: Interfacing an 8085-based CPU board with multiple peripheral cards using a shared 8-bit data bus.

IC Role / Device Role / Timing Role: Dual 4-bit buffer provides isolated, timing-controlled data path extension between CPU address/data lines and peripheral decoders.

Use Value: Enables clean signal fanout to four downstream devices without loading the CPU bus beyond TTL specifications.

Test Equipment Signal Routing

Programmable Logic Support

Use Scenario: Configurable signal path switching in automated test fixtures where stimulus and response lines must be dynamically enabled.

IC Role / Device Role / Timing Role: 3-state buffers serve as digitally controlled signal gates synchronized to test sequencer clocks.

Use Value: Allows single physical bus to route stimulus to Device Under Test (DUT) and return response without hardware reconfiguration.

Use Scenario: Driving LED status indicators and switch inputs from CPLD/FPGA I/O banks operating at 5 V TTL levels.

IC Role / Device Role / Timing Role: Level-shifting and current-boosting interface between programmable logic outputs and discrete 5 V loads.

Use Value: Provides robust 15 mA sink capability per output to directly drive LEDs or optocouplers without external transistors.

Equivalent & Alternatives

The following parts are listed as comparable options for similar non-inverting 3-state buffer applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LS244N	Octal (8-bit) non-inverting buffer with two independent 4-bit groups and identical OE control structure; same SOIC-20 and PDIP-20 packages available.	Offers double the channel count in larger packages; requires PCB layout change for pin count increase.	Select when higher channel density is needed and SOIC-20 or PDIP-20 footprints are acceptable.
SN74LS367AN	Inverting version (dual 4-bit inverting buffer); otherwise identical pinout, timing, and electrical specs in PDIP-16 package.	Used where logic inversion is required in signal path (e.g., active-high enable conversion); not functionally interchangeable without logic redesign.	Choose only if system-level logic requires inversion - verify truth table alignment before substitution.

Compared with SN74LS244N and SN74LS367AN, the SN74LS365AD provides optimal 4-bit non-inverting buffering in compact SOIC-16 format, balancing channel count, package size, and direct TTL compatibility for retrofit and maintenance of legacy digital systems.

Availability

SN74LS365AD is available at Aetrix Electronics and suitable for industrial data acquisition, legacy bus interface, test equipment signal routing, and programmable logic support requiring stable component supply and long-term obsolescence mitigation.

Supply support for SN74LS365AD includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader with over 90 years of analog and logic IC innovation, serving industrial, automotive, and communications markets.

The SN74LS365AD belongs to TI's legacy 74LS logic portfolio, engineered specifically for reliability and interoperability in commercial-grade TTL-based digital systems deployed from the 1970s through early 2000s.

FAQ

What is the function of SN74LS365AD in a digital system?

The SN74LS365AD functions as a dual 4-bit non-inverting buffer with 3-state outputs, enabling controlled signal routing on shared buses. Each of its two independent 4-bit groups (A1–A4 and B1–B4) responds to dedicated active-low output-enable inputs (1OE and 2OE), allowing precise timing of data flow without contention. This makes SN74LS365AD ideal for interfacing microcontrollers, memory, and peripherals in TTL-based architectures.

Is SN74LS365AD pin-compatible with SN74LS367AD?

No, SN74LS365AD is not pin-compatible with SN74LS367AD. While both are 16-pin SOIC devices with identical pin counts and package outlines, SN74LS367AD is an inverting buffer (outputs Y = NOT A), whereas SN74LS365AD is non-inverting (Y = A). Their input/output mappings differ at the functional level, and substituting one for the other without logic redesign will invert critical signals - potentially causing system failure. Always verify truth tables before interchange.

What is the maximum capacitive load SN74LS365AD can drive reliably?

SN74LS365AD is specified to drive up to 15 pF load capacitance with guaranteed 15 ns propagation delay (VCC = 5 V, TA = 25°C). At higher capacitances (e.g., >30 pF), delay increases nonlinearly and output rise/fall times degrade, risking setup/hold violations in synchronous systems. For loads exceeding 15 pF, add series termination or reduce trace length - SN74LS365AD itself does not include slew-rate control or driver strength adjustment.

Does SN74LS365AD support hot-swap or live-insertion?

No, SN74LS365AD does not support hot-swap or live-insertion. Its inputs lack powered-off protection, and outputs may enter undefined states during partial power-up. Applying signal inputs before VCC stabilizes risks latch-up or excessive current draw. For hot-swap applications, use purpose-built hot-swap controllers or buffers with Ioff (power-off protection) - SN74LS365AD lacks this feature entirely.

Can SN74LS365AD operate at 3.3 V?

No, SN74LS365AD is not rated for 3.3 V operation. It is a standard 74LS-family device requiring 4.75 V to 5.25 V supply. At 3.3 V, input thresholds become unreliable (VIH min drops below 2.0 V), output drive collapses (<1 mA source), and propagation delay exceeds specification. Use 74LVC or 74ALVC series for 3.3 V–compatible 3-state buffers - SN74LS365AD must be used strictly within its 5 V ±5% envelope.

SN74LS365AD Specifications

Product attributes: Attribute value

Manufacturer:: onsemi

Series:: 74LS

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tube

Product Status:: Obsolete

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 1

Number of Bits per Element:: 6

Input Type:: -

Output Type:: 3-State

Current - Output High, Low:: 2.6mA, 24mA

Voltage - Supply:: 4.75V ~ 5.25V

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

SN74LS365AD FAQ

1.How can I place an order for SN74LS365AD through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74LS365AD on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74LS365AD reliable?

The price and inventory of SN74LS365AD are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS365AD is usually 5 days.

3.What payment methods are accepted for SN74LS365AD?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS365AD transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74LS365AD?

SN74LS365AD orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74LS365AD order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74LS365AD?

For technical support, including SN74LS365AD datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS365AD requirements.

6.How does Aetrix verify that SN74LS365AD is sourced from the original manufacturer or authorized distributors?

All SN74LS365AD products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS365AD meets industry standards.

7.What is the process for return or replacement of SN74LS365AD?

All SN74LS365AD units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS365AD, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74LS365AD part is unused and in its original packaging.

Return procedure for SN74LS365AD:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

Tech Hub

2026-09-09 Counterfeit Electronic Components: How to Detect, Authenticate, and Test Suspect Parts

Counterfeit components can hide behind convincing markings and passing basic function tests. This engineering reference covers source traceability, external inspection, X-ray, XRF, electrical testing, …

2026-09-08 Obsolete Electronic Components: How to Source and Evaluate Replacements

A practical engineering and sourcing framework covering lifecycle verification, lifetime-buy calculations, replacement qualification, supplier checks and counterfeit-risk controls.

2026-09-07 TTL vs CMOS Logic Levels: 74HC and 74HCT Compatibility Explained

TTL and CMOS logic families differ in thresholds, loading, output drive, power and timing. This engineering guide compares 74HC and 74HCT, calculates noise margins and checks 3.3 V/5 V compatibility.

2026-09-04 Logic Level Shifter: How to Connect 3.3V and 5V Logic Safely

A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.

2026-09-03 74HC595 vs TPIC6B595: Output Drive, Pinout, Current, and Load Selection

The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…

2026-09-02 74HC595 Pinout, Timing, Output Current, and Applications

The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…

2026-09-01 Latch vs Flip-Flop: Timing, Differences and Design Choices

A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…

2026-08-30 D Latch Circuit: Truth Table, Timing, ICs and Applications

A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …

2026-08-28 SR Latch Explained: NOR and NAND Circuits, Truth Tables, and Applications

An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…

2026-08-27 Latch Circuit: SR and D Latches, Truth Tables, Timing, and Applications

Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…