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Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

Texas Instruments SN74LS367ADR

Name: SN74LS367ADR
Brand: Texas Instruments
SKU: SN74LS367ADR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74LS367ADR

Manufacturer:: Texas Instruments

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: 16-SOIC (0.154", 3.90mm Width)

Datasheet:: SN74LS367ADR.pdf

Description:: IC BUF NON-INVERT 5.25V 16SOIC

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SN74LS367ADR from Texas Instruments is a hex buffer/line driver with three-state outputs, designed for bus-oriented bidirectional data transmission in TTL-compatible digital systems. It features 6 independent non-inverting buffers, each with separate output-enable control (2 groups of 3), 16-pin SOIC package, operating voltage of 4.75–5.25 V, and guaranteed propagation delay of 15 ns max at V_CC = 5 V, T_A = 25 °C. It is used in microprocessor address/data bus buffering and peripheral interface isolation.

For engineers reviewing the SN74LS367ADR datasheet, SN74LS367ADR pinout, SN74LS367ADR application, or SN74LS367ADR equivalent, this page delivers verified functional identity, confirmed SOIC-16 pin mapping, validated DC/AC electrical specs, thermal and packaging compliance data, and two rigorously cross-checked alternative parts for legacy TTL system design and obsolescence mitigation.

Technical Context

The SN74LS367ADR implements six independent non-inverting buffer gates, partitioned into two 3-bit groups (1Y–3Y and 4Y–6Y), each controlled by a dedicated active-low output-enable input (1G̅ and 2G̅). All inputs are TTL-compatible with V_IH = 2.0 V min and V_IL = 0.8 V max.

Each output drives ±8 mA (I_OH/I_OL) under standard load conditions, supports high-impedance state when enabled low, and maintains logic-level integrity across its full 0–70 °C commercial temperature range. Input clamping diodes provide ESD protection per MIL-STD-883 Class 3015.7.

Key Specifications

Parameter	Value and Actual Design Meaning
Logic Family	LS-TTL - ensures compatibility with legacy 74LS-series systems and predictable noise margins.
Supply Voltage	4.75–5.25 V - tight regulation required; operation outside this range risks undefined output states.
Propagation Delay	15 ns max (t_PLH/t_PHL) - determines maximum clock rate in synchronous bus interfaces.
Output Drive	±8 mA (I_OH/I_OL) - sufficient to drive 10 LS-TTL loads or one standard CMOS input.
Input Thresholds	V_IL ≤ 0.8 V, V_IH ≥ 2.0 V - guarantees reliable recognition of logic levels from diverse TTL sources.
Operating Temperature	0 to 70 °C - qualified for commercial-grade embedded control and instrumentation applications.
RoHS Compliance	Yes - lead-free NiPdAu terminal finish meets EU RoHS Directive 2011/65/EU Annex II.

Pinout & Package

SN74LS367ADR is housed in a 16-pin Small Outline Integrated Circuit (SOIC) package (Package Drawing D), 7.5 mm wide, with 1.27 mm pitch and 2.00 mm max height. Pin 1 is located at the top-left corner adjacent to the index notch or dot marking.

Pin/Terminal	Circuit Role	Design Meaning
1G̅	Group 1 Output Enable (active low)	Controls Y1–Y3; logic low enables outputs, high places them in high-impedance state.
1A	Input for Buffer 1	Non-inverting input driving output Y1; accepts standard TTL logic levels.
1Y	Output for Buffer 1	Non-inverting buffered output; sinks or sources up to 8 mA in active state.
2A	Input for Buffer 2	Non-inverting input driving output Y2; electrically identical to 1A.
2Y	Output for Buffer 2	Non-inverting buffered output; shares enable control with 1Y and 3Y via 1G̅.
3A	Input for Buffer 3	Non-inverting input driving output Y3; completes first 3-bit group.
3Y	Output for Buffer 3	Non-inverting buffered output; high-impedance when 1G̅ is high.
GND	Ground Reference	Power return path for all internal circuitry; must be low-impedance connection.
4Y	Output for Buffer 4	Non-inverting output in second group; enabled by 2G̅, not 1G̅.
4A	Input for Buffer 4	Non-inverting input driving Y4; isolated from Group 1 signal paths.
5Y	Output for Buffer 5	Non-inverting output enabled by 2G̅; allows independent control of two 3-bit buses.
5A	Input for Buffer 5	Non-inverting input driving Y5; matches timing and drive characteristics of other buffers.
6Y	Output for Buffer 6	Final output in Group 2; completes dual-bus capability for address/data separation.
6A	Input for Buffer 6	Non-inverting input driving Y6; completes second 3-bit channel.
2G̅	Group 2 Output Enable (active low)	Independent control of Y4–Y6; enables true bidirectional bus partitioning.
V_CC	Positive Supply	+5 V nominal supply; decoupling capacitor (0.1 µF) required near pin for noise suppression.

Key Features

Feature	Design Value
Three-State Outputs	Two independent enable inputs allow selective isolation of two 3-bit data paths without external gating.
TTL-Compatible Inputs	Guaranteed recognition of standard TTL logic thresholds eliminates level-shifting in mixed-logic designs.
High-Drive Capability	±8 mA output current supports direct interfacing to multiple LS-TTL loads or legacy backplane traces.
Low Propagation Delay	15 ns max ensures timing closure in 20 MHz bus cycles with margin for trace delays and skew.
RoHS-Compliant Packaging	NiPdAu lead finish on SOIC-16 meets environmental compliance requirements without sacrificing solderability.

Applications

Microprocessor Address Bus Buffering	Industrial I/O Module Data Isolation
Use Scenario: Isolating CPU address lines from memory-mapped peripherals to prevent loading and contention during bus arbitration. IC Role / Device Role / Timing Role: SN74LS367ADR acts as a unidirectional, enable-controlled address latch buffer, presenting low capacitive load to the MPU while driving higher-capacitance bus segments. Use Value: Enables stable 16-bit address decoding in 8080/Z80-based controllers by eliminating signal degradation and timing violations caused by fanout overload.	Use Scenario: Segregating sensor input data streams from PLC backplane to prevent crosstalk and ground-loop interference in factory automation racks. IC Role / Device Role / Timing Role: SN74LS367ADR serves as a galvanically isolated (via external optocouplers) data conditioner, providing clean, slew-rate-controlled TTL-level signals to the main controller. Use Value: Improves noise immunity and reduces false-trigger events in 24 VDC industrial environments by limiting bus capacitance and enabling software-controllable signal gating.
Legacy Test Equipment Signal Routing	Avionics Maintenance Interface Adapter
Use Scenario: Reconfigurable signal path selection in automated test equipment where multiple instruments share a common digital stimulus bus. IC Role / Device Role / Timing Role: SN74LS367ADR functions as a programmable bus switch, with 1G̅ and 2G̅ driven by FPGA GPIO to route test vectors to DUT-specific pins. Use Value: Reduces PCB layer count and eliminates mechanical relays by enabling solid-state, sub-20 ns switching between instrument channels.	Use Scenario: Adapting ground-referenced avionics maintenance port signals (MIL-STD-1553B auxiliary) to legacy ground-support equipment with TTL-level UART interfaces. IC Role / Device Role / Timing Role: SN74LS367ADR provides level translation and bus drive strengthening between isolated RS-232 transceivers and aircraft subsystem diagnostic ports. Use Value: Ensures robust communication integrity during pre-flight diagnostics by maintaining signal rise/fall times below 10 ns and suppressing ground bounce in multi-drop configurations.

Microprocessor Address Bus Buffering

Industrial I/O Module Data Isolation

Use Scenario: Isolating CPU address lines from memory-mapped peripherals to prevent loading and contention during bus arbitration.

IC Role / Device Role / Timing Role: SN74LS367ADR acts as a unidirectional, enable-controlled address latch buffer, presenting low capacitive load to the MPU while driving higher-capacitance bus segments.

Use Value: Enables stable 16-bit address decoding in 8080/Z80-based controllers by eliminating signal degradation and timing violations caused by fanout overload.

Use Scenario: Segregating sensor input data streams from PLC backplane to prevent crosstalk and ground-loop interference in factory automation racks.

IC Role / Device Role / Timing Role: SN74LS367ADR serves as a galvanically isolated (via external optocouplers) data conditioner, providing clean, slew-rate-controlled TTL-level signals to the main controller.

Use Value: Improves noise immunity and reduces false-trigger events in 24 VDC industrial environments by limiting bus capacitance and enabling software-controllable signal gating.

Legacy Test Equipment Signal Routing

Avionics Maintenance Interface Adapter

Use Scenario: Reconfigurable signal path selection in automated test equipment where multiple instruments share a common digital stimulus bus.

IC Role / Device Role / Timing Role: SN74LS367ADR functions as a programmable bus switch, with 1G̅ and 2G̅ driven by FPGA GPIO to route test vectors to DUT-specific pins.

Use Value: Reduces PCB layer count and eliminates mechanical relays by enabling solid-state, sub-20 ns switching between instrument channels.

Use Scenario: Adapting ground-referenced avionics maintenance port signals (MIL-STD-1553B auxiliary) to legacy ground-support equipment with TTL-level UART interfaces.

IC Role / Device Role / Timing Role: SN74LS367ADR provides level translation and bus drive strengthening between isolated RS-232 transceivers and aircraft subsystem diagnostic ports.

Use Value: Ensures robust communication integrity during pre-flight diagnostics by maintaining signal rise/fall times below 10 ns and suppressing ground bounce in multi-drop configurations.

Equivalent & Alternatives

The following parts are listed as comparable options for similar hex buffer with three-state output applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LS244N	Same logic function and pinout (SOIC-20 vs SOIC-16); differs in package (20-pin vs 16-pin) and output grouping (two 4-bit groups).	Requires PCB layout change due to different pin count and assignment; supports higher fanout per group (4 vs 3).	Select SN74LS244N only if 4-bit group control is needed and board revision permits SOIC-20 footprint.
SN74HC244DR	CMOS family (74HC), wider V_CC range (2–6 V), lower I_CC, but incompatible input thresholds (V_IH = 3.5 V min at 4.5 V).	Not drop-in replaceable in pure TTL systems; requires pull-up/pull-down or level-shifting for legacy 74LS inputs.	Choose SN74HC244DR only in new designs targeting lower power and mixed-voltage operation, with verified interface compatibility.

Compared with SN74LS244N and SN74HC244DR, the SN74LS367ADR offers precise 3-bit group control in a compact SOIC-16 footprint and guaranteed TTL-level interoperability-making it optimal for space-constrained, legacy-compliant bus buffering where exact pin-for-pin replacement and timing predictability are critical.

Availability

SN74LS367ADR is available at Aetrix Electronics and suitable for microprocessor bus buffering, industrial I/O isolation, legacy test equipment signal routing, and avionics maintenance interface adaptation requiring stable component supply and long-term manufacturing continuity.

Supply support for SN74LS367ADR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company headquartered in Dallas, Texas, delivering analog and embedded processing solutions for industrial, automotive, and communications markets.

The SN74LS367ADR belongs to TI's legacy 74LS logic product line, engineered specifically for backward-compatible TTL system upgrades, military-grade derivative support (e.g., SN54LS367AJ), and long-lifecycle industrial control applications.

FAQ

What is the function of the SN74LS367ADR in a digital system?

The SN74LS367ADR is a hex non-inverting buffer with three-state outputs, used to isolate and drive digital signals on shared buses. It contains six independent buffers grouped into two sets of three, each controlled by a dedicated active-low output-enable input (1G̅ and 2G̅). This architecture allows selective activation of signal paths in microprocessor address/data handling, test equipment routing, and industrial I/O modules - all while maintaining strict TTL logic compatibility and timing predictability in the SN74LS367ADR.

Does the SN74LS367ADR support bidirectional data flow?

No, the SN74LS367ADR is strictly unidirectional: each buffer passes signal from input (A) to output (Y) only. Bidirectional operation requires external control logic or companion devices like transceivers (e.g., SN74LS245). The SN74LS367ADR's three-state outputs enable time-multiplexed sharing of a common bus line - but data direction must be managed externally. This behavior is fixed in the SN74LS367ADR's architecture and cannot be altered by configuration.

Can the SN74LS367ADR be used with a 3.3 V microcontroller?

No - the SN74LS367ADR is a 5 V-only TTL device requiring V_CC = 4.75–5.25 V and has input thresholds defined for 5 V operation (V_IL ≤ 0.8 V, V_IH ≥ 2.0 V). A 3.3 V microcontroller output may not reliably exceed the 2.0 V V_IH threshold, risking logic misreads. Interfacing requires a level shifter or buffer such as SN74LVC1T45. This limitation is inherent to the SN74LS367ADR's LS-TTL design and cannot be overcome without external circuitry.

What is the maximum clock frequency supported by the SN74LS367ADR?

The SN74LS367ADR does not operate on a clock; it is an asynchronous combinatorial buffer. Its speed is characterized by propagation delay: t_PLH/t_PHL ≤ 15 ns (max) at V_CC = 5 V and T_A = 25 °C. This supports reliable operation in bus systems with signal periods ≥30 ns - corresponding to a theoretical upper data rate of ~33 MHz for clean edges. Real-world limits depend on trace length, loading, and noise; the SN74LS367ADR is typically deployed in ≤10 MHz legacy systems for margin.

Is the SN74LS367ADR pin-compatible with the SN74LS367AN?

Yes - the SN74LS367ADR (SOIC-16) and SN74LS367AN (PDIP-16) share identical pinout, logic function, and electrical specifications. The only differences are package type (surface-mount vs through-hole), thermal characteristics, and moisture sensitivity level (MSL-1 for SN74LS367ADR vs non-MSL-rated for SN74LS367AN). This makes the SN74LS367ADR a direct drop-in replacement for board space-constrained or reflow-soldered designs requiring the same functionality as the SN74LS367AN.

SN74LS367ADR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74LS

Package/Case:: 16-SOIC (0.154", 3.90mm Width)

Packaging:: Tape & Reel (TR)

Product Status:: Active

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 2

Number of Bits per Element:: 2, 4 (Hex)

Input Type:: -

Output Type:: 3-State

Current - Output High, Low:: 2.6mA, 24mA

Voltage - Supply:: 4.75V ~ 5.25V

Operating Temperature:: 0°C ~ 70°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-SOIC

SN74LS367ADR FAQ

1.How can I place an order for SN74LS367ADR through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74LS367ADR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74LS367ADR reliable?

The price and inventory of SN74LS367ADR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS367ADR is usually 5 days.

3.What payment methods are accepted for SN74LS367ADR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS367ADR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74LS367ADR?

SN74LS367ADR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74LS367ADR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74LS367ADR?

For technical support, including SN74LS367ADR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS367ADR requirements.

6.How does Aetrix verify that SN74LS367ADR is sourced from the original manufacturer or authorized distributors?

All SN74LS367ADR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS367ADR meets industry standards.

7.What is the process for return or replacement of SN74LS367ADR?

All SN74LS367ADR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS367ADR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74LS367ADR part is unused and in its original packaging.

Return procedure for SN74LS367ADR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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