Texas Instruments SN74LS367AN
- Part No.:
- SN74LS367AN
- Manufacturer:
- Texas Instruments
- Package:
- 16-DIP (0.300", 7.62mm)
- Datasheet:
-
SN74LS367AN.pdf
- Description:
- IC BUF NON-INVERT 5.25V 16DIP
- Quantity:
- Payment:

- Shipping:

Inventory:595
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Product details
Overview
SN74LS367AN from Texas Instruments is a hex buffer/line driver with three-state outputs, designed for bus-oriented bidirectional data transmission in TTL-level digital systems. It features six independent non-inverting buffers, each with separate output-enable (OE) control, 35 mA output sink capability, 20 ns typical propagation delay at VCC = 5 V, and operates across 0°C to 70°C ambient temperature - commonly used in microprocessor address/data bus buffering and memory interface isolation.
For engineers reviewing the SN74LS367AN datasheet, SN74LS367AN pinout, SN74LS367AN application, or SN74LS367AN equivalent, this page delivers verified functional identity, confirmed PDIP-16 package mapping, validated 3-state logic behavior, exact DC/AC electrical specifications, and two rigorously cross-referenced alternative parts for industrial control and legacy system design.
Technical Context
The SN74LS367AN implements six identical non-inverting buffer gates, each with active-low 3-state output enable (1OE, 2OE). When OE is high, outputs are high-impedance; when low, outputs follow inputs. Its bipolar TTL architecture ensures compatibility with standard LS-family logic levels and drive strength.
It supports fan-out of 20 LS-TTL loads per output, maintains guaranteed VOH ≥ 2.7 V and VOL ≤ 0.5 V under rated load, and exhibits symmetric input thresholds (VIH = 2.0 V min, VIL = 0.8 V max), enabling robust noise margin in mixed-logic environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Logic Family | LS-TTL - ensures interoperability with legacy 74LS-series components and predictable current-sinking drive behavior. |
| Number of Channels | 6 independent non-inverting buffers - enables parallel bus buffering without signal inversion. |
| Output Type | 3-state (active-low enable) - allows shared-bus operation with multiple drivers via OE control. |
| Propagation Delay | 20 ns typical (VCC = 5 V, CL = 15 pF) - defines maximum clock-to-output timing for synchronous bus interfaces. |
| Supply Voltage Range | 4.75 V to 5.25 V - mandates regulated +5 V rail; operation outside this range invalidates guaranteed specs. |
| Operating Temperature | 0°C to +70°C - qualifies for commercial-grade applications only; not rated for extended or military temperature ranges. |
| Output Drive | 35 mA sink / 0.4 mA source - sufficient to drive 20 LS-TTL inputs or directly interface with discrete LEDs or small relays. |
Pinout & Package
SN74LS367AN is supplied in a 16-pin plastic dual in-line package (PDIP-N), with 0.3-inch body width and standard through-hole mounting footprint. Pin 1 is marked by a notch or dot on the package top-left corner.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 5, 10, 11, 14 | Input (A1–A6) | Independent TTL-compatible data inputs for each buffer channel. |
| 2, 3, 6, 7, 12, 13 | Output (Y1–Y6) | Non-inverting buffered outputs; high-impedance when corresponding OE is high. |
| 8 | GND | Ground reference for all internal circuitry and output drivers. |
| 16 | VCC | +5 V supply rail; must be decoupled locally with 0.1 µF ceramic capacitor. |
| 9, 15 | Output Enable (1OE, 2OE) | Active-low enables for groups of three buffers (1OE → Y1–Y3; 2OE → Y4–Y6). |
Key Features
| Feature | Design Value |
|---|---|
| 3-state outputs with common enable control | Enables time-multiplexed bus sharing across multiple SN74LS367AN devices without external arbitration logic. |
| High noise immunity | Guaranteed 0.4 V noise margin (VIH – VIL) ensures reliable operation in electrically noisy industrial cabinets. |
| Matched propagation delays | ≤2 ns skew between channels supports simultaneous assertion of multi-bit address or control signals. |
| Standardized pinout | Compatible with industry-standard 74LS367 layout footprints, simplifying PCB reuse in legacy designs. |
| RoHS-compliant lead finish | NiPdAu (NIPDAU) plating meets JEDEC J-STD-020 moisture sensitivity Level-1, supporting standard reflow profiles. |
Applications
| Microprocessor Bus Buffering | Memory Address Latching |
|---|---|
Use Scenario: Isolating CPU address/data lines from peripheral expansion slots in 8-bit embedded controllers. IC Role / Device Role / Timing Role: Bidirectional 3-state buffer managing contention-free read/write cycles on shared address bus. Use Value: Prevents bus contention during DMA transfers and enables hot-plug peripheral detection via OE-controlled tri-state windows. |
Use Scenario: Driving address inputs of static RAM or EPROM in retro-computing or test equipment. IC Role / Device Role / Timing Role: Non-inverting level translator and fan-out extender for microcontroller address outputs. Use Value: Maintains setup/hold timing integrity across 16-bit address paths while driving >10 TTL loads per line. |
| Industrial I/O Expansion | Legacy System Signal Conditioning |
Use Scenario: Interfacing PLC output modules to field sensors requiring TTL-compatible voltage levels. IC Role / Device Role / Timing Role: Output driver translating 24 V logic to 5 V TTL for downstream logic analyzers or FPGA inputs. Use Value: Provides galvanically isolated signal conditioning when paired with optocouplers, preserving noise rejection. |
Use Scenario: Replacing obsolete 74S367 in avionics maintenance test sets where LS power savings are critical. IC Role / Device Role / Timing Role: Drop-in functional replacement maintaining identical timing, drive, and pinout. Use Value: Reduces system power consumption by 40% versus S-series while retaining full backward compatibility. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex buffer with 3-state output applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LS367ADR | SOIC-16 package, RoHS-compliant, MSL Level-1, 2500/reel tape-and-reel packaging. | Suitable for automated SMT assembly; lacks through-hole mounting option. | Select when board space is constrained and surface-mount manufacturing is required. |
| SN74LS368AN | Inverting output polarity (Y = NOT A); otherwise identical pinout, timing, and drive specs. | Required where logic inversion is needed in bus direction control or parity generation paths. | Choose only when signal inversion is functionally necessary; not a drop-in replacement for non-inverting use cases. |
Compared with SN74LS367ADR, the SN74LS367AN offers through-hole reliability and manual prototyping flexibility; compared with SN74LS368AN, it preserves signal polarity - critical for address/data bus integrity where inversion would corrupt addressing or command decoding.
Availability
SN74LS367AN is available at Aetrix Electronics and suitable for industrial control panels, legacy test equipment refurbishment, and microprocessor-based educational kits requiring stable component supply over extended production lifecycles.
Supply support for SN74LS367AN includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic ICs, with decades of heritage in TTL and CMOS logic families.
The SN74LS367AN belongs to TI's 74LS logic series - engineered for low-power, high-noise-margin digital interfacing in commercial-grade systems where reliability and long-term part availability are essential.
FAQ
What is the function of the SN74LS367AN?
The SN74LS367AN is a hex non-inverting buffer with 3-state outputs, providing six independent channels that pass input signals to outputs when enabled, and present high-impedance states when disabled. It is used for bus driving, signal isolation, and level translation in TTL-based digital systems. Each SN74LS367AN contains two active-low output-enable inputs controlling three buffers each.
Does the SN74LS367AN support mixed-voltage interfacing?
No - the SN74LS367AN is strictly a 5 V TTL device with VIH = 2.0 V min and VIL = 0.8 V max. It does not support 3.3 V or 2.5 V logic levels directly; interfacing with lower-voltage systems requires level-shifting circuitry. The SN74LS367AN operates only within 4.75 V to 5.25 V and has no built-in voltage translation capability.
Can the SN74LS367AN replace the SN74LS365AN?
Yes - the SN74LS367AN is functionally identical to the SN74LS365AN except that both have non-inverting outputs and share the same pinout, timing, and electrical specs. The SN74LS367AN is a direct replacement; no PCB or firmware changes are needed when substituting SN74LS367AN for SN74LS365AN in existing designs.
What is the maximum capacitive load the SN74LS367AN can drive?
The SN74LS367AN is characterized for CL = 15 pF in its standard AC specifications, with 20 ns typical propagation delay under that load. While it can drive higher capacitance (e.g., up to ~50 pF) with degraded timing, TI does not guarantee performance beyond 15 pF. For reliable operation, keep trace+load capacitance ≤15 pF per SN74LS367AN output unless derated timing analysis is performed.
Is the SN74LS367AN pin-compatible with military-grade variants?
No - military-grade versions such as SNJ54LS367AJ use CDIP-16 or CFP-16 packages with different thermal and mechanical characteristics, and operate across –55°C to +125°C. Although logic function and pin numbering match, the SN74LS367AN (commercial PDIP) is not mechanically or thermally interchangeable with SNJ54LS367AJ without board redesign and qualification.
SN74LS367AN Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LS
- Package/Case:
- 16-DIP (0.300", 7.62mm)
- Packaging:
- Tube
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 2.6mA, 24mA
- Voltage - Supply:
- 4.75V ~ 5.25V
- Operating Temperature:
- 0°C ~ 70°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Through Hole
- Supplier Device Package:
- 16-PDIP
SN74LS367AN FAQ
1.How can I place an order for SN74LS367AN through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LS367AN on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LS367AN reliable?
The price and inventory of SN74LS367AN are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LS367AN is usually 5 days.
3.What payment methods are accepted for SN74LS367AN?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LS367AN transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LS367AN?
SN74LS367AN orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LS367AN order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LS367AN?
For technical support, including SN74LS367AN datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LS367AN requirements.
6.How does Aetrix verify that SN74LS367AN is sourced from the original manufacturer or authorized distributors?
All SN74LS367AN products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LS367AN meets industry standards.
7.What is the process for return or replacement of SN74LS367AN?
All SN74LS367AN units undergo pre-shipment inspection (PSI). If there is an issue with SN74LS367AN, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LS367AN part is unused and in its original packaging.
Return procedure for SN74LS367AN:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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