Texas Instruments SN74LV123ADRG4

Overview

SN74LV123ADRG4 from Texas Instruments is a dual retriggerable monostable multivibrator IC with Schmitt-trigger inputs, operating from 2 V to 5.5 V supply, delivering ≤11 ns propagation delay at 5 V, ±1% pulse-duration matching between channels, and programmable output pulse width via external R/C network. It serves as a precision timing generator in digital signal conditioning and interrupt synchronization circuits.

For engineers reviewing the SN74LV123ADRG4 datasheet, SN74LV123ADRG4 pinout, SN74LV123ADRG4 application, or SN74LV123ADRG4 equivalent, key selection criteria include its retriggerable pulse control, Ioff partial-power-down support, mixed-voltage interface capability, and guaranteed glitch-free power-up reset - all critical for embedded timing integrity in noise-prone environments.

Technical Context

The SN74LV123ADRG4 integrates two independent monostable multivibrators, each triggered by edge-sensitive logic on A/B/CLR inputs with Schmitt hysteresis (≥0.3×VCC), enabling robust operation with slow or noisy signals. Pulse duration is externally set via Rext/Cext network, supporting tw = K × RT × CT where K = 1.0 for CT ≥ 1000 pF.

It supports three trigger modes per channel: falling edge on A (with B = L), rising edge on B (with A = H), or simultaneous A = L/B = H with CLR rising edge. The CLR input overrides active pulses, forcing immediate Q/Q transition, and Ioff circuitry disables outputs during power-down to prevent backflow current.

Key Specifications

Pinout & Package

SN74LV123ADRG4 is packaged in a 16-pin SOIC (D) body measuring 6.00 mm × 9.90 mm, with standard 1.27 mm pitch and gull-wing leads compatible with automated SMT assembly.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar monostable multivibrator applications.

Compared with SN74LVC123A and 74HC123, SN74LV123ADRG4 uniquely combines Ioff protection, Schmitt-trigger robustness, and ±1% pulse matching - making it the preferred choice for mission-critical timing in automotive infotainment, NAS controllers, and embedded PCs requiring deterministic power sequencing.

Availability

SN74LV123ADRG4 is available at Aetrix Electronics and suitable for AV receivers, DVD players, and embedded PCs requiring stable component supply, long-lifecycle support, and consistent parametric performance across temperature extremes.

Supply support for SN74LV123ADRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog and embedded processing technologies, with over 90 years of innovation in precision timing, power management, and logic solutions.

The SN74LV123ADRG4 belongs to TI's LV logic family, designed specifically for low-voltage, high-noise-immunity digital timing applications in consumer electronics, industrial controls, and computing infrastructure.

FAQ

What is the minimum external capacitance supported for timing on SN74LV123ADRG4?

The SN74LV123ADRG4 supports external timing capacitors down to 100 pF with verified accuracy. For values below 1000 pF, the multiplier factor K deviates from 1.0 and must be determined from Figure 3 in the datasheet. At 100 pF and 10 kΩ, typical pulse duration is 90–110 µs. Using smaller capacitors requires careful layout to minimize stray capacitance, as parasitic effects dominate below 50 pF - SN74LV123ADRG4 is not characterized for sub-50 pF operation.

Does SN74LV123ADRG4 support true dual-edge triggering on the same input pair?

No, SN74LV123ADRG4 does not support simultaneous rising-and-falling edge detection on a single A/B pair. Each channel uses complementary edge sensitivity: A is falling-edge active (when B = L), B is rising-edge active (when A = H). To detect both edges of one signal, route it to separate channels - e.g., invert the signal and apply to A of Channel 1 and B of Channel 2. This configuration is explicitly validated in the functional block diagram and timing examples of the SN74LV123ADRG4 datasheet.

How does the Ioff feature behave during partial power-down of SN74LV123ADRG4?

When VCC drops below 0.8 V, the Ioff circuitry in SN74LV123ADRG4 actively disables all outputs, limiting leakage current to ≤5 µA per I/O pin regardless of input voltage (0–5.5 V). This prevents back-driving powered-down sections of the system. The feature is tested per JESD78 Class II and remains effective even if inputs float or are driven by live 5 V sources - a key differentiator from standard HC or AHC logic that lacks this protection.

Can SN74LV123ADRG4 generate asymmetrical Q and Q output pulse widths?

No, SN74LV123ADRG4 produces inherently symmetrical Q and Q outputs: both exhibit identical pulse duration (tw) and ±1% matching between channels. The outputs are true logical complements - any observed asymmetry indicates layout imbalance (e.g., unequal trace lengths or loads) or measurement error. The datasheet specifies Δtw ≤ ±1% between Q and Q, confirming matched internal timing paths. For intentional asymmetry, external gating or cascaded stages are required.

What is the maximum recommended value for Rext when using SN74LV123ADRG4 at 5 V supply?

The SN74LV123ADRG4 datasheet validates Rext up to 100 kΩ at VCC = 5 V, yielding pulse durations up to ~10 ms with 100 pF Cext. Beyond 100 kΩ, leakage current (±25 µA max) introduces timing error exceeding ±5%. TI recommends limiting Rext to ≤50 kΩ for production designs requiring <±2% accuracy. Higher values increase susceptibility to humidity-induced drift and board contamination - SN74LV123ADRG4's electrical characteristics table confirms stable operation only within the 1–100 kΩ range.