Texas Instruments SN74LV126ADBR
- Part No.:
- SN74LV126ADBR
- Manufacturer:
- Texas Instruments
- Package:
- 14-SSOP (0.209", 5.30mm Width)
- Datasheet:
-
SN74LV126ADBR.pdf
- Description:
- IC BUF NON-INVERT 5.5V 14SSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,495
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Product details
Overview
SN74LV126ADBR from Texas Instruments is a quadruple 3-state bus buffer gate IC designed for level-translating, low-noise digital interface applications in mixed-voltage systems. It operates from 2V to 5.5V VCC, delivers 6.5ns max propagation delay at 5V, supports Ioff for live insertion and partial power-down, and features 5.5V-tolerant inputs - enabling reliable use in server backplanes and network switch data paths.
For engineers reviewing the SN74LV126ADBR datasheet, SN74LV126ADBR pinout, SN74LV126ADBR application, or SN74LV126ADBR equivalent, key selection criteria include its 14-pin SSOP (DB) package, independent per-channel 3-state control via dedicated OE inputs, guaranteed 35mA output drive, ±1µA input leakage, and compatibility with 2.5V/3.3V/5V logic domains without external level shifters.
Technical Context
The SN74LV126ADBR implements four independent noninverting buffers, each with a dedicated active-high output-enable (OE) input controlling high-impedance state entry. Its CMOS design ensures balanced rise/fall times and low ground bounce (<0.8V typical at 3.3V), minimizing signal integrity issues on shared buses.
It supports mixed-mode voltage operation: inputs tolerate up to 5.5V regardless of VCC (2–5.5V), enabling down-translation from higher-voltage controllers to lower-voltage peripherals. The Ioff feature disables all outputs during power-off, preventing back-drive current and enabling hot-plug capability.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2V to 5.5V - enables interoperability across 2.5V, 3.3V, and 5V logic domains without level shifters |
| tpd (max) | 6.5ns at VCC = 5V, CL = 15pF - ensures sub-7ns timing margin for high-speed bus buffering |
| IOL/IOH | ±16mA at VCC = 4.5–5.5V - drives standard TTL loads and moderate capacitive stubs |
| Ioff | ±5µA at VCC = 0V - blocks current flow during partial power-down, protecting powered sections |
| VIH/VIL | VCC × 0.7 / VCC × 0.3 - provides noise-immune switching thresholds scaling with supply |
| Ci | 1.6pF at VCC = 3.3V - minimizes capacitive loading on driving sources |
| ESD Rating | ±2000V HBM - meets industrial-grade robustness requirements for board-level handling |
Pinout & Package
SN74LV126ADBR uses a 14-pin SSOP (Shrink Small Outline Package) with 0.65mm pitch, 6.2mm × 7.8mm body size, and gull-wing leads. Pin 1 is marked by a beveled corner or dot; the package is RoHS-compliant with NIPDAU lead finish and MSL Level-1 rating.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 4OE, 3OE, 2OE | Active-high output enable (4×) | Each independently controls one buffer's 3-state output; tie low to disable, high to pass A→Y |
| 1A–4A | Buffer input (4×) | 5.5V-tolerant CMOS inputs accepting voltages beyond VCC for level translation |
| 1Y–4Y | Buffer output (4×) | Noninverting, totem-pole outputs with 35mA sink/source capability and low ground bounce |
| GND (Pin 7) | Ground reference | Common return path for all internal circuitry; must be low-inductance connection |
| VCC (Pin 14) | Positive supply | Single supply powering all four buffers; requires local 0.1µF bypass capacitor |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (2–5.5V) | Enables single-bom support across 2.5V, 3.3V, and 5V system rails without redesign |
| 5.5V-tolerant inputs | Accepts 5V signals while operating at 2.5V or 3.3V VCC, eliminating external translators |
| Ioff protection | Prevents current backflow when VCC = 0V, supporting hot-swap and partial-power-down modes |
| Low dynamic noise (VOLP < 0.8V) | Reduces ground bounce on shared PCB planes, critical for multi-buffer bus stability |
| 125°C operating temperature | Validated for extended thermal environments in telecom infrastructure and industrial control |
Applications
| Server Backplane Interface | Network Switch Control Bus |
|---|---|
|
Use Scenario: Isolating and driving configuration/status signals between 5V management MCU and 3.3V FPGA-based packet processing modules. IC Role / Device Role / Timing Role: Bidirectional bus buffer with independent OE control per channel, translating 5V control signals down to 3.3V logic levels. Use Value: Eliminates need for discrete level shifters; 6.5ns tpd ensures timing compliance with PCIe/PCI-X sideband signaling. |
Use Scenario: Driving LED status indicators and fan control lines from a 3.3V microcontroller in a 1U rack-mount switch. IC Role / Device Role / Timing Role: Low-noise, high-drive buffer providing clean 3.3V outputs to multiple parallel loads. Use Value: 35mA per output sustains brightness across 8+ LEDs; Ioff prevents back-drive when controller resets. |
| Electronic Point-of-Sale Terminal | Set-Top Box HDMI CEC Interface |
|
Use Scenario: Buffering keyboard scan matrix and display backlight PWM signals in a dual-rail (5V/3.3V) retail terminal. IC Role / Device Role / Timing Role: Quad noninverting gate with per-channel 3-state control, enabling time-multiplexed peripheral access. Use Value: Independent OE pins allow dynamic isolation of unused peripherals, reducing system EMI and power leakage. |
Use Scenario: Interfacing a 5V CEC controller to 3.3V HDMI PHY in a consumer set-top box with legacy IR remote support. IC Role / Device Role / Timing Role: Voltage-tolerant bus buffer ensuring CEC signal integrity across rail boundaries. Use Value: 5.5V-tolerant inputs accept 5V CEC pulses directly; low VOLP prevents false triggering on shared ground. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC126A | Lower VCC min (1.65V), faster tpd (5.3ns @ 3.3V), but no 5.5V input tolerance | Suitable only in fully 3.3V or lower systems; cannot replace SN74LV126ADBR where 5V inputs exist | Select when operating exclusively below 3.3V and speed >6.5ns is required |
| 74LVX126M | Same 2–3.6V VCC range and 5.5V input tolerance, but obsolete and limited availability | Legacy drop-in replacement with identical pinout and function, but no long-term supply assurance | Use only for legacy repair; not recommended for new designs due to obsolescence risk |
Compared with SN74LV126ADBR, SN74LVC126A offers higher speed at lower voltage but sacrifices 5V input compatibility, while 74LVX126M matches functionality but lacks production continuity - making SN74LV126ADBR the optimal choice for new 2–5.5V mixed-rail designs requiring assured supply and full voltage flexibility.
Availability
SN74LV126ADBR is available at Aetrix Electronics and suitable for server backplane interfaces, network switch control buses, and electronic point-of-sale terminals requiring stable component supply, long-lifecycle support, and guaranteed SSOP packaging consistency.
Supply support for SN74LV126ADBR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 90 years of innovation in industrial, automotive, and communications markets.
The SN74LV126ADBR belongs to TI's LV logic family, engineered for robust mixed-voltage interfacing in high-reliability infrastructure equipment - emphasizing wide supply range, Ioff safety, and noise-controlled switching.
FAQ
What is the maximum operating temperature for SN74LV126ADBR?
The SN74LV126ADBR is rated for operation from –40°C to +125°C ambient temperature, validated per JEDEC JESD78 and confirmed in TI's SCES131J datasheet Section 5.3. This extended range supports deployment in thermally demanding environments such as telecom base stations and industrial PLCs where the SN74LV126ADBR serves as a critical bus interface element.
Does SN74LV126ADBR support hot-swap insertion?
Yes, SN74LV126ADBR supports live insertion via its Ioff feature: when VCC = 0V, input and output leakage remains ≤±5µA, preventing back-drive current into powered system sections. This behavior is explicitly characterized in Section 5.5 of the SN74LV126ADBR datasheet and enables safe hot-plug operation in modular server and networking hardware.
What is the pinout compatibility between SN74LV126ADBR and SN74LV126ADR?
SN74LV126ADBR (SSOP-14, DB package) and SN74LV126ADR (SOIC-14, D package) share identical pin numbering, signal assignment, and logic function per Table 4-1 and Figure 4-1 of the SN74LV126ADBR datasheet. However, their physical footprints differ - DB has 0.65mm pitch and 6.2mm × 7.8mm body, while D uses 1.27mm pitch and 8.65mm × 6mm - so PCB layout changes are required for substitution.
Can SN74LV126ADBR drive a 50pF load at 10MHz without signal degradation?
Yes, SN74LV126ADBR maintains 8.5ns max tpd and controlled edge rates at CL = 50pF and VCC = 5V (Section 5.8), and its typical output ground bounce stays below 0.8V at 3.3V (Section 1). These specs confirm stable operation into 50pF loads at 10MHz clock rates, as verified in TI's Application Report SCBA004 on CMOS bus interface design using SN74LV126ADBR.
Is SN74LV126ADBR RoHS compliant and what is its moisture sensitivity level?
Yes, SN74LV126ADBR is RoHS-compliant (lead-free, NiPdAu finish) and carries an MSL Level-1 rating (unlimited floor life at ≤30°C/60% RH), per TI's PACKAGE OPTION ADDENDUM. This allows standard SMT assembly without baking, simplifying manufacturing for high-volume production of devices using SN74LV126ADBR in consumer and industrial applications.
SN74LV126ADBR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LV
- Package/Case:
- 14-SSOP (0.209", 5.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 16mA, 16mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SSOP
SN74LV126ADBR FAQ
1.How can I place an order for SN74LV126ADBR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LV126ADBR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LV126ADBR reliable?
The price and inventory of SN74LV126ADBR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LV126ADBR is usually 5 days.
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Once your SN74LV126ADBR order is processed, you will receive an email with the shipment details and tracking number.
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5.How can I obtain technical support or documentation for SN74LV126ADBR?
For technical support, including SN74LV126ADBR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LV126ADBR requirements.
6.How does Aetrix verify that SN74LV126ADBR is sourced from the original manufacturer or authorized distributors?
All SN74LV126ADBR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LV126ADBR meets industry standards.
7.What is the process for return or replacement of SN74LV126ADBR?
All SN74LV126ADBR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LV126ADBR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LV126ADBR part is unused and in its original packaging.
Return procedure for SN74LV126ADBR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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