Texas Instruments SN74LV126APW
- Part No.:
- SN74LV126APW
- Manufacturer:
- Texas Instruments
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74LV126APW.pdf
- Description:
- IC BUF NON-INVERT 5.5V 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:3,419
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Product details
Overview
SN74LV126APW from Texas Instruments is a quadruple 3-state bus buffer gate IC designed for voltage-level translation and bus isolation in mixed-voltage digital systems. It operates across 2V–5.5V VCC, delivers ≤6.5ns propagation delay at 5V, supports Ioff for live insertion, and features 5.5V-tolerant inputs - enabling use in server backplanes, network switch control buses, and set-top-box I/O expansion.
For engineers reviewing the SN74LV126APW datasheet, SN74LV126APW pinout, SN74LV126APW application, or SN74LV126APW equivalent, key selection considerations include its 14-pin TSSOP package, independent per-channel 3-state enable logic, low ground bounce (<0.8V at 3.3V), and compatibility with 2.5V/3.3V/5V mixed-signal interfacing.
Technical Context
The SN74LV126APW implements four independent noninverting buffers, each with dedicated active-high output-enable (OE) control. Each channel transitions to high-impedance when OE is low, and passes A→Y when OE is high - supporting bidirectional bus arbitration and hot-swap-safe signal routing.
Its CMOS design enables down-translation (e.g., 5V input → 3.3V VCC output), while Ioff protection prevents current flow during partial power-down. Electrical characteristics are specified across –40°C to +125°C, with latch-up immunity >250mA per JESD17.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2V to 5.5V - supports interoperability across 2.5V, 3.3V, and 5V logic domains without level shifters |
| tpd (max) | 6.5ns at VCC = 5V, CL = 15pF - ensures timing-critical bus buffering in high-speed control paths |
| Ioff | ±5µA at VCC = 0V - enables safe live insertion and back-drive protection during system power sequencing |
| VIH/VIL | VIH = 0.7×VCC, VIL = 0.3×VCC - provides noise-immune switching thresholds scalable with supply voltage |
| Output Drive | ±16mA at VCC = 4.5V - sufficient for driving 15pF loads over 10cm traces without external termination |
| Input Voltage Tolerance | 0V to 5.5V - allows 5V signals to be safely applied while operating from 3.3V or 2.5V supplies |
| Operating Temperature | –40°C to +125°C - qualified for industrial and extended-temperature embedded applications |
Pinout & Package
TSSOP-14 (PW) package: 5mm × 6.4mm body, 0.65mm pitch, 1.2mm max height, lead-free (NIPDAU/Sn) finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 4OE, 3OE, 2OE | Active-high output enable (4 independent inputs) | Each controls one buffer channel; tie low via pulldown resistor for power-up high-Z state |
| 1A–4A | Buffer input (4 channels) | 5.5V-tolerant CMOS inputs; accept logic levels up to 5.5V regardless of VCC |
| 1Y–4Y | Noninverting buffered output (4 channels) | 3-state outputs with controlled VOLP/VOHV; drive capability scales with VCC |
| VCC | Positive supply | Single supply rail powers all four buffers; bypass with 0.1µF ceramic capacitor near pin |
| GND | Ground reference | Common return for all I/O and supply currents; connect to low-impedance ground plane |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (2V–5.5V) | Enables single device deployment across multiple voltage domains in multi-rail systems |
| Independent per-channel 3-state control | Allows selective bus segment isolation without affecting other data lanes |
| Ioff protection | Prevents damaging current flow during hot-plug events or partial power-down sequences |
| Low dynamic ground bounce (<0.8V) | Reduces simultaneous switching noise in dense PCB layouts with shared ground paths |
| 5.5V-tolerant inputs | Eliminates need for external level translators when interfacing legacy 5V peripherals |
Applications
| Server Backplane Interface | Network Switch Control Bus |
|---|---|
|
Use Scenario: Isolating management controller (BMC) GPIOs from hot-swappable line card status lines in 1U rack servers. IC Role / Device Role / Timing Role: Bidirectional 3-state buffer providing voltage translation between 3.3V BMC and 5V line card presence detection circuits. Use Value: Prevents bus contention during card insertion/removal and eliminates need for discrete level-shifting components. |
Use Scenario: Driving configuration registers and LED indicators on modular Ethernet switch fabric cards. IC Role / Device Role / Timing Role: Low-skew, low-noise buffer enabling synchronized register writes across multiple PHYs under 125°C ambient conditions. Use Value: Ensures clean signal edges into capacitive loads (≥50pF), reducing EMI and improving register write reliability. |
| Set-Top Box I/O Expansion | Electronic Point-of-Sale (POS) Terminal |
|
Use Scenario: Extending GPIO count from main SoC to IR receiver, HDMI CEC, and USB hub control lines. IC Role / Device Role / Timing Role: Voltage-flexible bus buffer translating 1.8V SoC outputs to 3.3V peripheral interface levels. Use Value: Maintains signal integrity across mixed-voltage subsystems while meeting consumer-grade thermal limits (≤85°C). |
Use Scenario: Interfacing 5V legacy barcode scanner and receipt printer signals with modern 3.3V microcontroller UARTs. IC Role / Device Role / Timing Role: Input-tolerant buffer decoupling legacy peripherals from MCU I/O pins during power sequencing. Use Value: Enables direct connection without external clamping diodes or resistive dividers, reducing BOM cost and board area. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC126APW | Lower VCC min (1.65V), faster tpd (5.3ns @ 3.3V), but no Ioff support | Not suitable for live-insertion scenarios requiring power-down isolation | Choose when operating exclusively at 3.3V and maximum speed is critical; avoid where partial power-down occurs |
| 74LVX126M | Same VCC range (2–3.6V), SOIC-14 only, higher ICC (50µA vs. 20µA) | Limited to 3.6V max VCC; not rated for 5V operation or 5.5V-tolerant inputs | Select only for legacy 3.3V-only designs with SOIC footprint constraints; verify 5V tolerance not required |
Compared with SN74LV126APW, SN74LVC126APW offers higher speed but sacrifices Ioff-based system robustness, while 74LVX126M lacks 5V compatibility and consumes more quiescent current - making SN74LV126APW the optimal choice for mixed-voltage, hot-swap-capable industrial interfaces.
Availability
SN74LV126APW is available at Aetrix Electronics and suitable for server backplane interface, network switch control bus, and electronic point-of-sale terminal applications requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SN74LV126APW includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog and embedded processing solutions, with decades of expertise in logic, interface, and power management ICs.
The SN74LV126A product line was developed to address voltage translation and bus isolation needs in industrial, communications, and consumer electronics - delivering robust 3-state performance across wide supply ranges and harsh thermal environments.
FAQ
What is the maximum operating temperature for SN74LV126APW?
The SN74LV126APW is rated for operation from –40°C to +125°C ambient temperature, fully specified across this range per JEDEC standards. This makes SN74LV126APW suitable for under-hood automotive modules, industrial PLCs, and telecom equipment deployed in uncontrolled environments where thermal margins are critical.
Does SN74LV126APW support live insertion or hot-swap applications?
Yes, SN74LV126APW supports live insertion via its Ioff feature, which limits leakage current to ±5µA when VCC = 0V. This prevents back-driving and current flow during partial power-down - a key requirement for SN74LV126APW deployment in hot-pluggable server blades and modular network hardware.
Can SN74LV126APW interface 5V signals with a 3.3V supply?
Yes, SN74LV126APW accepts input voltages up to 5.5V regardless of VCC level, enabling direct connection of 5V peripherals to a 3.3V-powered system. When VCC = 3.3V, SN74LV126APW outputs swing from 0V to 3.3V, providing safe, translator-free down-translation - a core function of the SN74LV126APW.
What is the recommended bypass capacitor for SN74LV126APW?
A 0.1µF ceramic capacitor placed as close as possible to the VCC pin (Pin 14) and GND (Pin 7) is recommended for SN74LV126APW. For systems with multiple supply rails or high-frequency noise, paralleling a 1µF tantalum or X7R MLCC improves broadband decoupling - essential for maintaining SN74LV126APW signal integrity in noisy industrial environments.
Is SN74LV126APW pin-compatible with other TSSOP-14 bus buffers?
SN74LV126APW uses the standard 14-pin TSSOP (PW) footprint defined by JEDEC MO-153, matching mechanical dimensions and pinout of SN74LVC126APW and 74LVX126M. However, electrical behavior differs - SN74LV126APW's 2V–5.5V range and Ioff are not replicated in those alternatives, so functional validation is required before substitution.
SN74LV126APW Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LV
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 16mA, 16mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
SN74LV126APW FAQ
1.How can I place an order for SN74LV126APW through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LV126APW on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LV126APW reliable?
The price and inventory of SN74LV126APW are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LV126APW is usually 5 days.
3.What payment methods are accepted for SN74LV126APW?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LV126APW transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LV126APW?
SN74LV126APW orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LV126APW order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LV126APW?
For technical support, including SN74LV126APW datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LV126APW requirements.
6.How does Aetrix verify that SN74LV126APW is sourced from the original manufacturer or authorized distributors?
All SN74LV126APW products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LV126APW meets industry standards.
7.What is the process for return or replacement of SN74LV126APW?
All SN74LV126APW units undergo pre-shipment inspection (PSI). If there is an issue with SN74LV126APW, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LV126APW part is unused and in its original packaging.
Return procedure for SN74LV126APW:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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