Texas Instruments SN74LV126APWR
- Part No.:
- SN74LV126APWR
- Manufacturer:
- Texas Instruments
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74LV126APWR.pdf
- Description:
- IC BUF NON-INVERT 5.5V 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:2,207
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Product details
Overview
SN74LV126APWR from Texas Instruments is a quadruple 3-state bus buffer gate IC designed for voltage-level translation and bus isolation in mixed-voltage digital systems. It operates across 2V–5.5V VCC, delivers ≤6.5ns propagation delay at 5V, supports Ioff for live insertion, and features 5.5V-tolerant inputs - enabling use in server backplanes and network switch data paths where signal integrity and power sequencing matter.
For engineers reviewing the SN74LV126APWR datasheet, SN74LV126APWR pinout, SN74LV126APWR application, or SN74LV126APWR equivalent, this page provides verified functional identity, TSSOP-14 package mapping, confirmed 3-state timing specs, and real-world interface design context - all grounded in TI's SCES131J production data sheet (April 2024 revision).
Technical Context
The SN74LV126APWR implements four independent noninverting buffers, each with dedicated active-high output-enable (OE) control and true 3-state output behavior. Its CMOS architecture enables bidirectional voltage translation: inputs accept up to 5.5V regardless of VCC (2V–5.5V), while outputs swing rail-to-rail between GND and VCC.
It integrates Ioff circuitry that disables all outputs and isolates I/O terminals during partial power-down, preventing current backflow and enabling hot-plug capability. Ground bounce (VOLP) and undershoot (VOHV) are characterized at <0.8V and >2.3V respectively under 3.3V operation - critical for minimizing signal integrity issues in high-speed bus environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2V to 5.5V - supports mixed-voltage system interfacing (e.g., 5V logic driving 3.3V bus) |
| tpd (max) | 6.5ns at VCC = 5V, CL = 15pF - ensures timing compliance in sub-150MHz bus applications |
| Ioff | ±5µA at VCC = 0V - enables safe live insertion and partial power-down without bus contention |
| Input Voltage Tolerance | Up to 5.5V independent of VCC - allows 5V-tolerant inputs on 2.5V/3.3V supplies without level shifters |
| Output Drive | ±16mA at VCC = 4.5–5.5V - sufficient for driving moderate capacitive loads (≤50pF) on PCB traces |
| Operating Temperature | –40°C to +125°C - qualified for industrial and extended-temperature embedded networking hardware |
| ESD Rating (HBM) | ±2000V - meets JEDEC JS-001 for robust handling in automated assembly environments |
Pinout & Package
TSSOP-14 (PW) package: 5.0mm × 6.4mm body, 0.65mm pitch, 1.2mm max height, RoHS-compliant NiPdAu/Sn lead finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1OE, 4OE, 3OE, 2OE | Active-high output enable (4 independent) | Each controls one buffer; low = high-Z output, high = A→Y pass-through |
| 1A–4A | Buffer input (4 channels) | 5.5V-tolerant CMOS inputs; accept logic levels independent of VCC |
| 1Y–4Y | Buffer output (4 channels) | CMOS outputs swing 0V to VCC; support bus sharing via 3-state control |
| VCC (Pin 14) | Positive supply | Single supply powers all buffers; range 2V–5.5V defines logic thresholds and drive strength |
| GND (Pin 7) | Ground reference | Return path for all I/O and internal logic; must be low-impedance for noise control |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range (2V–5.5V) | Enables single device deployment across 2.5V, 3.3V, and 5V subsystems without redesign |
| 5.5V-tolerant inputs | Eliminates external level translators when interfacing higher-voltage controllers to lower-VCC buses |
| Ioff partial-power-down protection | Prevents back-drive current and latch-up during hot-swap or asymmetric power sequencing |
| Low ground bounce & undershoot | VOLP < 0.8V / VOHV > 2.3V at 3.3V - reduces EMI and improves signal fidelity on shared lines |
| Latch-up immunity | >250mA per JESD17 - ensures reliability in noisy industrial or telecom environments |
Applications
| Server Backplane Interface | Network Switch Data Path |
|---|---|
|
Use Scenario: Isolating control signals between 5V management MCU and 3.3V FPGA-based packet processing module on a multi-layer server motherboard. IC Role / Device Role / Timing Role: SN74LV126APWR acts as a directionally controlled, voltage-translating bus buffer - enabling clean signal handoff without level-shifter components. Use Value: Eliminates need for discrete level translators; 6.5ns tpd preserves timing margin in 100MHz control bus; Ioff prevents corruption during FPGA reconfiguration. |
Use Scenario: Driving parallel status indicators (LEDs) and configuration registers from a 3.3V switch ASIC while maintaining compatibility with legacy 5V peripheral interfaces. IC Role / Device Role / Timing Role: SN74LV126APWR serves as a 3-state fanout buffer - allowing multiple ASICs to share a common configuration bus without contention. Use Value: 5.5V-tolerant inputs accept 5V register writes; 3-state outputs prevent bus conflicts during hot-swap of line cards; ±16mA drive supports LED direct-drive. |
| Electronic Point-of-Sale Terminal | Set-Top Box HDMI Control Bus |
|
Use Scenario: Buffering I²C and GPIO signals between a 3.3V ARM SoC and 5V payment card reader module in a retail POS terminal. IC Role / Device Role / Timing Role: SN74LV126APWR functions as a bidirectional voltage translator and bus isolator - ensuring signal integrity during power-up sequencing and peripheral insertion. Use Value: Ioff blocks current flow when reader is unplugged; 2V–5.5V operation accommodates both SoC and reader supply rails; 125°C rating supports enclosed thermal environments. |
Use Scenario: Managing DDC/CEC control lines between a 3.3V media processor and 5V HDMI PHY in a consumer set-top box. IC Role / Device Role / Timing Role: SN74LV126APWR provides isolated, slew-controlled buffering for low-speed control buses - preventing crosstalk and ground bounce in dense HDMI subsystem layouts. Use Value: Low VOLP/VOHV minimizes DDC signal distortion; TSSOP-14 footprint saves board space vs. SOIC; RoHS-compliant finish meets consumer electronics requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC126APW | Lower VCC range (1.65V–3.6V); faster tpd (5.1ns @ 3.3V); no 5.5V input tolerance | Restricted to 3.3V-only systems; unsuitable for 5V-tolerant interfaces or mixed-voltage backplanes | Select only if full 5V compatibility is unnecessary and speed is prioritized over voltage flexibility |
| 74LVX126M | Same VCC range (2V–3.6V); 5V-tolerant inputs; SOIC-14 only; slightly higher tpd (7.5ns @ 3.3V) | Limited to 3.6V max VCC; lacks 5.5V operation; larger SOIC footprint increases board area | Choose when TSSOP-14 is unavailable and 3.6V upper limit suffices; verify thermal performance in compact enclosures |
Compared with SN74LV126APWR, SN74LVC126APW trades 5.5V input tolerance for higher speed in 3.3V-only designs, while 74LVX126M offers pin-compatible SOIC packaging but sacrifices 5.5V operation and board-space efficiency - making SN74LV126APWR the optimal choice for mixed-voltage, space-constrained, hot-plug-capable applications.
Availability
SN74LV126APWR is available at Aetrix Electronics and suitable for server backplanes, network switch data paths, and electronic point-of-sale terminals requiring stable component supply, long-term lifecycle support, and RoHS-compliant TSSOP packaging.
Supply support for SN74LV126APWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of expertise in high-reliability interface ICs.
The SN74LV126A family was engineered for robust bus interfacing in industrial, telecom, and computing infrastructure - emphasizing voltage translation, 3-state control, and power sequencing resilience.
FAQ
What is the maximum operating voltage for SN74LV126APWR?
The SN74LV126APWR supports a VCC range of 2V to 5.5V, with absolute maximum ratings up to 7V. Operation beyond 5.5V violates recommended conditions and risks parametric degradation. The 5.5V upper limit enables compatibility with standard 5V logic while maintaining safe margins for transient spikes.
Does SN74LV126APWR support hot-plug insertion?
Yes, SN74LV126APWR supports live insertion via its Ioff feature: when VCC = 0V, all I/O terminals enter high-impedance state with leakage ≤±5µA, preventing back-drive current and bus contention during partial power-down - a key requirement for modular telecom and server hardware.
What is the propagation delay of SN74LV126APWR at 3.3V supply?
At VCC = 3.3V ±0.3V and CL = 15pF, the SN74LV126APWR exhibits a typical propagation delay (tpd) of 5ns and a maximum of 9.5ns. This value is measured from A input to Y output under defined load and temperature conditions per TI's SCES131J datasheet.
Can SN74LV126APWR translate 5V logic signals to a 2.5V bus?
Yes - SN74LV126APWR accepts input voltages up to 5.5V regardless of VCC. When powered at 2.5V, its 5.5V-tolerant inputs safely receive 5V logic levels, and outputs swing 0V to 2.5V, providing reliable down-translation without external components.
What package type does SN74LV126APWR use?
SN74LV126APWR uses the TSSOP-14 (PW) package: 5.0mm × 6.4mm body, 0.65mm lead pitch, 1.2mm max height, with NiPdAu/Sn lead finish and MSL Level-1 rating - optimized for high-density PCB layouts and automated surface-mount assembly.
SN74LV126APWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LV
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 16mA, 16mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
SN74LV126APWR FAQ
1.How can I place an order for SN74LV126APWR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LV126APWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LV126APWR reliable?
The price and inventory of SN74LV126APWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LV126APWR is usually 5 days.
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SN74LV126APWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LV126APWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LV126APWR?
For technical support, including SN74LV126APWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LV126APWR requirements.
6.How does Aetrix verify that SN74LV126APWR is sourced from the original manufacturer or authorized distributors?
All SN74LV126APWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LV126APWR meets industry standards.
7.What is the process for return or replacement of SN74LV126APWR?
All SN74LV126APWR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LV126APWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LV126APWR part is unused and in its original packaging.
Return procedure for SN74LV126APWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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