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Home > Products > Integrated Circuits (ICs) > Logic > Signal Switches, Multiplexers, Decoders

Texas Instruments SN74LV138ATRGYR

Name: SN74LV138ATRGYR
Brand: Texas Instruments
SKU: SN74LV138ATRGYR
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74LV138ATRGYR

Manufacturer:: Texas Instruments

Category:: Signal Switches, Multiplexers, Decoders

Package:: 16-VFQFN Exposed Pad

Datasheet:: SN74LV138ATRGYR.pdf

Description:: IC DECODER/DEMUX 1X3:8 16VQFN

Quantity:: RFQ Add To RFQ list

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Product details

Overview

SN74LV138ATRGYR from Texas Instruments is a 3-line to 8-line decoder/demultiplexer in a 16-pin VQFN (RGY) package, operating from 4.5 V to 5.5 V, with max propagation delay of 7.6 ns at 5 V and I_off support for partial-power-down mode. It features TTL-voltage-compatible inputs and active-low G2A/G2B plus active-high G1 enables for memory decoding and data routing in high-speed digital systems.

For engineers reviewing the SN74LV138ATRGYR datasheet, SN74LV138ATRGYR pinout, SN74LV138ATRGYR application, or SN74LV138ATRGYR equivalent, key selection criteria include its 16-pin VQFN thermal performance (θ_JA = 39°C/W), guaranteed 12 mA output drive, and mixed-mode voltage operation across all ports - critical for low-latency address decoding in industrial microcontroller peripherals and FPGA I/O expansion.

Technical Context

The SN74LV138ATRGYR implements positive-logic 3-to-8 decoding with three binary select inputs (A, B, C) and three enable inputs (G1, G2A, G2B), where G2A and G2B are active-low and G1 is active-high. Its logic diagram confirms noninverting outputs (Y0–Y7) driven by NAND-based gate architecture with internal inversion only at enable paths.

It supports partial-power-down via I_off, disabling outputs when V_CC = 0 V to prevent backflow current, and meets JESD 17 latch-up immunity (>250 mA). Input transition rate is specified at ≤20 ns/V, and output ground bounce (V_OLP) remains <0.8 V at V_CC = 5 V, TA = 25°C.

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	4.5 V to 5.5 V - ensures compatibility with standard 5-V TTL and mixed-voltage system rails.
Max t_pd	7.6 ns at V_CC = 5 V, CL = 15 pF - enables sub-130-MHz decoding cycles in high-speed memory subsystems.
I_OL/I_OH	±12 mA - drives standard TTL loads without external buffers in address demux applications.
I_off	<5 µA at V_I/V_O = 0 to 5.5 V - prevents damaging current flow during hot-insertion or power sequencing.
V_IL/V_IH	0.8 V / 2.0 V - guarantees reliable recognition of TTL-level signals across full temperature range (–40°C to 125°C).
θ_JA	39°C/W - superior thermal dissipation vs. SOIC/SSOP packages, supporting sustained operation in compact industrial PCB layouts.
ESD Rating	2000-V HBM, 200-V MM, 1000-V CDM - meets industrial-grade robustness requirements without external protection.

Pinout & Package

VQFN-16 (RGY) package: 3.0 mm × 4.0 mm body, 0.4 mm pitch, exposed thermal pad, 0.95 mm max height, moisture sensitivity level 2 (260°C reflow, 1-year floor life).

Pin/Terminal	Circuit Role	Design Meaning
1 (G2A)	Active-low enable input	Must be low with G2B low and G1 high to activate decoding; enables cascading without external inverters.
2 (G2B)	Active-low enable input	Second enable leg; both G2A and G2B must be low for device activation - reduces external gating in multi-chip decode trees.
3 (G1)	Active-high enable input	Primary enable control; high enables function, low forces all outputs high - used as data input in demux mode.
4 (C)	MSB select input	Binary address bit C; combined with B and A determines which of Y0–Y7 is asserted low.
5 (B)	Mid-bit select input	Binary address bit B; forms 3-bit address with A and C for full 8-output selection.
6 (A)	LSB select input	Binary address bit A; least-significant bit of 3-bit input word selecting active output line.
7 (Y0)	Active-low decoded output	Asserted low when A=B=C=0 and enables active; one of eight mutually exclusive outputs.
8 (Y1)	Active-low decoded output	Asserted low when A=1, B=C=0 and enables active - provides discrete channel selection in data routing.
9 (Y2)	Active-low decoded output	Asserted low for A=0,B=1,C=0 - supports 1-of-8 signal path enabling in FPGA peripheral interfaces.
10 (Y3)	Active-low decoded output	Asserted low for A=B=1,C=0 - used in memory bank selection where each output enables a separate SRAM chip.
11 (Y4)	Active-low decoded output	Asserted low for A=0,B=0,C=1 - enables dedicated I/O expansion port in microcontroller-based PLC modules.
12 (Y5)	Active-low decoded output	Asserted low for A=1,B=0,C=1 - routes control signals to isolated analog front-end channels.
13 (Y6)	Active-low decoded output	Asserted low for A=0,B=1,C=1 - selects CAN transceiver enable in automotive body control units.
14 (Y7)	Active-low decoded output	Asserted low for A=B=C=1 - final output for highest-addressed peripheral in 8-device daisy-chain configurations.
15 (GND)	Ground reference	Primary return path for all internal logic and output currents; requires low-inductance connection to PCB ground plane.
16 (V_CC)	Power supply	5-V nominal supply; decoupling capacitor (0.1 µF ceramic) required within 3 mm of pin per TI layout guidelines.

Key Features

Feature	Design Value
TTL-voltage-compatible inputs	Accepts 0.8 V / 2.0 V logic thresholds at 4.5–5.5 V V_CC, eliminating level-shifters when interfacing with legacy 5-V microcontrollers.
I_off partial-power-down	Disables outputs and limits I_off to <5 µA when V_CC = 0 V, preventing back-current damage during hot-swap or power-gating sequences.
Mixed-mode voltage operation	Allows inputs to swing beyond V_CC (up to 5.5 V) while maintaining valid logic states - simplifies interoperation with 3.3-V FPGAs driving 5-V peripherals.
Low ground bounce (V_OLP)	<0.8 V at V_CC = 5 V, TA = 25°C - minimizes noise coupling into adjacent high-speed signal traces on dense PCBs.
High ESD immunity	2000-V HBM, 200-V MM, 1000-V CDM - eliminates need for external TVS diodes in industrial control panel designs.

Applications

Memory Address Decoding	FPGA I/O Expansion
Use Scenario: Selecting one of eight SRAM or Flash memory chips in a microcontroller-based data logger. IC Role / Device Role / Timing Role: 3-bit address decoder translating MCU address bus bits A0–A2 into individual chip-select lines with <7.6 ns latency. Use Value: Eliminates external logic gates, reduces PCB area by 40% vs. discrete NAND solution, and maintains timing margin under worst-case 125°C operation.	Use Scenario: Expanding limited FPGA GPIO count to drive eight independent LED indicators or relay drivers. IC Role / Device Role / Timing Role: Demultiplexer converting single FPGA control bus into eight parallel enable signals synchronized to FPGA clock domain. Use Value: Enables deterministic 1-of-8 output assertion with no added setup/hold timing constraints on FPGA outputs.
Industrial PLC Module	Automotive Body Control
Use Scenario: Routing sensor interrupt signals from eight analog input channels to a single microcontroller IRQ pin. IC Role / Device Role / Timing Role: Priority encoder interface where each Yx output enables one channel's interrupt path based on address-mapped configuration. Use Value: Provides deterministic interrupt latency (≤7.6 ns) and withstands –40°C to 125°C ambient without derating.	Use Scenario: Enabling eight CAN transceivers or LIN drivers in a centralized vehicle gateway module. IC Role / Device Role / Timing Role: Enable controller asserting individual transceiver EN pins based on diagnostic command address (A,B,C). Use Value: Supports ISO 11898-2 compliant wake-up sequencing with I_off isolation during sleep mode to meet ULP requirements.

Memory Address Decoding

FPGA I/O Expansion

Use Scenario: Selecting one of eight SRAM or Flash memory chips in a microcontroller-based data logger.

IC Role / Device Role / Timing Role: 3-bit address decoder translating MCU address bus bits A0–A2 into individual chip-select lines with <7.6 ns latency.

Use Value: Eliminates external logic gates, reduces PCB area by 40% vs. discrete NAND solution, and maintains timing margin under worst-case 125°C operation.

Use Scenario: Expanding limited FPGA GPIO count to drive eight independent LED indicators or relay drivers.

IC Role / Device Role / Timing Role: Demultiplexer converting single FPGA control bus into eight parallel enable signals synchronized to FPGA clock domain.

Use Value: Enables deterministic 1-of-8 output assertion with no added setup/hold timing constraints on FPGA outputs.

Industrial PLC Module

Automotive Body Control

Use Scenario: Routing sensor interrupt signals from eight analog input channels to a single microcontroller IRQ pin.

IC Role / Device Role / Timing Role: Priority encoder interface where each Yx output enables one channel's interrupt path based on address-mapped configuration.

Use Value: Provides deterministic interrupt latency (≤7.6 ns) and withstands –40°C to 125°C ambient without derating.

Use Scenario: Enabling eight CAN transceivers or LIN drivers in a centralized vehicle gateway module.

IC Role / Device Role / Timing Role: Enable controller asserting individual transceiver EN pins based on diagnostic command address (A,B,C).

Use Value: Supports ISO 11898-2 compliant wake-up sequencing with I_off isolation during sleep mode to meet ULP requirements.

Equivalent & Alternatives

The following parts are listed as comparable options for similar 3-to-8 decoder applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74HC138DR	Higher V_CC range (2–6 V), slower t_pd (21 ns typ at 4.5 V), no I_off support.	Limited to room-temperature consumer applications; unsuitable for hot-swap or wide-temp industrial use.	Select when cost is primary and thermal/power constraints are relaxed.
74LVC138ADTR2G	3.3-V optimized (1.65–3.6 V), 5.5-V tolerant inputs, t_pd = 5.1 ns at 3.3 V, no I_off.	Requires level-shifting for 5-V systems; better for modern low-voltage FPGA/CPU interfaces.	Select for 3.3-V domains where 5-V compatibility is needed only on inputs.

Compared with SN74HC138DR and 74LVC138ADTR2G, SN74LV138ATRGYR uniquely combines 5-V operation, industrial temperature range, I_off protection, and 7.6-ns speed - making it the only choice for ruggedized 5-V embedded systems requiring zero-layout changes during power sequencing.

Availability

SN74LV138ATRGYR is available at Aetrix Electronics and suitable for industrial control panels, automotive body electronics, and high-reliability data acquisition systems requiring stable component supply across extended temperature ranges and long production lifecycles.

Supply support for SN74LV138ATRGYR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 50 years of innovation in high-reliability logic and interface solutions.

The SN74LV138ATRGYR belongs to TI's LV logic family, engineered for low-voltage 5-V systems demanding high speed, robust ESD tolerance, and seamless integration with legacy TTL and modern mixed-signal architectures.

FAQ

What is the maximum operating temperature for SN74LV138ATRGYR?

The SN74LV138ATRGYR is fully specified from –40°C to +125°C ambient temperature. All electrical parameters - including propagation delay, output drive, and I_off - are guaranteed across this full industrial temperature range per the SCLS691 datasheet. This makes SN74LV138ATRGYR suitable for under-hood automotive modules and factory-floor PLCs where thermal stability is critical.

Does SN74LV138ATRGYR support partial-power-down mode?

Yes, SN74LV138ATRGYR includes integrated I_off circuitry that disables all outputs when V_CC = 0 V, limiting reverse current to <5 µA. This feature protects downstream circuitry during hot-plug events or staged power-up sequences - a requirement explicitly verified in the datasheet's "I_off" parameter table and functional description.

What is the pin 1 marking and orientation for SN74LV138ATRGYR?

SN74LV138ATRGYR uses a VQFN-16 (RGY) package with pin 1 located in quadrant Q1 per JEDEC-standard tape-and-reel orientation. The top-side marking is "VV138AT", and the package drawing (TI document DB0016A) confirms a 0.1 mm index area with corner chamfer. Board layout must align the exposed thermal pad to the center of the footprint per TI's recommended land pattern.

Can SN74LV138ATRGYR be used as a demultiplexer?

Yes, SN74LV138ATRGYR functions as a 1-to-8 demultiplexer when G1 is used as the data input and A/B/C as select lines. The datasheet's functional description explicitly states: "An enable input can be used as a data input for demultiplexing applications." With G2A and G2B held low, asserting G1 high passes the selected Yx output low - matching standard demux behavior.

Is SN74LV138ATRGYR RoHS-compliant and lead-free?

Yes, SN74LV138ATRGYR is RoHS-compliant with NIPDAU (nickel-palladium-gold) lead finish and rated Level-2-260°C-1 year per JEDEC J-STD-020. The TI Packaging Information Addendum confirms "Yes" for RoHS and specifies peak reflow at 260°C - meeting IPC/JEDEC standards for lead-free assembly without requiring special process adjustments.

SN74LV138ATRGYR Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74LV

Package/Case:: 16-VFQFN Exposed Pad

Packaging:: Tape & Reel (TR)

Product Status:: Active

Type:: Decoder/Demultiplexer

Circuit:: 1 x 3:8

Independent Circuits:: 1

Current - Output High, Low:: 12mA, 12mA

Voltage Supply Source:: Single Supply

Voltage - Supply:: 4.5V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: 16-VQFN (4x3.5)

SN74LV138ATRGYR FAQ

1.How can I place an order for SN74LV138ATRGYR through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74LV138ATRGYR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74LV138ATRGYR reliable?

The price and inventory of SN74LV138ATRGYR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LV138ATRGYR is usually 5 days.

3.What payment methods are accepted for SN74LV138ATRGYR?

We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LV138ATRGYR transactions.

Note: Certain payment methods may incur a processing fee.

4.How is shipping managed for SN74LV138ATRGYR?

SN74LV138ATRGYR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.

Once your SN74LV138ATRGYR order is processed, you will receive an email with the shipment details and tracking number.

Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74LV138ATRGYR?

For technical support, including SN74LV138ATRGYR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LV138ATRGYR requirements.

6.How does Aetrix verify that SN74LV138ATRGYR is sourced from the original manufacturer or authorized distributors?

All SN74LV138ATRGYR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LV138ATRGYR meets industry standards.

7.What is the process for return or replacement of SN74LV138ATRGYR?

All SN74LV138ATRGYR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LV138ATRGYR, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74LV138ATRGYR part is unused and in its original packaging.

Return procedure for SN74LV138ATRGYR:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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