Texas Instruments SN74LV1T125DBVRG4
- Part No.:
- SN74LV1T125DBVRG4
- Manufacturer:
- Texas Instruments
- Package:
- SC-74A, SOT-753
- Datasheet:
-
SN74LV1T125DBVRG4.pdf
- Description:
- IC BUF NON-INVERT 5.5V SOT23-5
- Quantity:
- Payment:

- Shipping:

Inventory:1,983
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74LV1T125DBVRG4 from Texas Instruments is a single-supply CMOS buffer gate with 3-state output, designed for bidirectional logic-level translation between 1.2 V to 5.0 V domains. It operates across 1.8 V–5.5 V VCC, delivers up to 8 mA output drive at 5 V, supports 50 MHz switching at 3.3 V, and features 5.0 V-tolerant inputs-enabling use in mixed-voltage I/O interfacing between microcontrollers and legacy peripherals in portable and telecom systems.
For engineers reviewing the SN74LV1T125DBVRG4 datasheet, SN74LV1T125DBVRG4 pinout, SN74LV1T125DBVRG4 application, or SN74LV1T125DBVRG4 equivalent, key selection criteria include its single-channel 3-state buffer architecture, SOT-23-5 package compatibility, VIH/VIL thresholds optimized for up/down translation, guaranteed operation from –40°C to +125°C, and support for industrial-grade voltage domain bridging without external biasing.
Technical Context
The SN74LV1T125DBVRG4 implements an LVxT-family enhanced-input buffer with reduced VIH/VIL thresholds enabling reliable up-translation (e.g., 1.8 V → 3.3 V at 3.3 V VCC) and down-translation (e.g., 5.0 V → 3.3 V at 3.3 V VCC). Its output is rail-to-rail referenced to VCC, and input pins tolerate up to 5.5 V independent of supply voltage.
It uses balanced CMOS push-pull outputs capable of sourcing/sinking matched currents (8 mA/–8 mA at 5 V), with propagation delays as low as 2.7 ns (5 V, 15 pF) and enable/disable times under 6.5 ns. The device includes internal clamp diodes and meets JESD17 latch-up immunity (>250 mA).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.8 V to 5.5 V - enables direct interface across 1.8 V, 2.5 V, 3.3 V, and 5 V logic domains |
| Input Voltage Tolerance | Up to 5.5 V - allows safe connection of higher-voltage signals without external level-shifting circuitry |
| Output Drive | 8 mA at 5 V VCC - sufficient to drive moderate capacitive loads and reduce signal reflections on PCB traces |
| Max Switching Frequency | 50 MHz at 3.3 V VCC - supports high-speed control signaling in real-time embedded interfaces |
| Propagation Delay | 2.7 ns typical (5 V, 15 pF) - ensures timing-critical paths meet setup/hold requirements in fast digital systems |
| Operating Temperature | –40°C to +125°C - qualified for automotive under-hood, industrial control, and extended-temperature portable applications |
| ESD Rating (HBM) | ±2000 V - provides robust handling during board assembly and field service without additional protection |
Pinout & Package
SOT-23-5 (DBV) package: 2.90 mm × 2.80 mm footprint, 1.6 mm body width, 1.45 mm height, lead-free NiPdAu finish (G4 suffix), moisture sensitivity level 1, reflow compatible up to 260°C.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OE | Active-low output enable | Drives Y into high-impedance state when low; must not float - tie to VCC or GND via pull-up/down resistor |
| 2 - A | Buffer input | Accepts 1.2 V–5.5 V logic signals; VIH/VIL thresholds scale with VCC for automatic level adaptation |
| 3 - GND | Ground reference | Return path for all internal logic and output current; requires low-inductance connection to system ground plane |
| 4 - Y | 3-state buffered output | CMOS-compatible output referenced to VCC; sinks/sources up to 8 mA; 5.0 V tolerant only in high-Z state |
| 5 - VCC | Positive supply | Single power rail defining output logic levels; bypass with 0.1 µF ceramic capacitor placed within 2 mm |
Key Features
| Feature | Design Value |
|---|---|
| Single-supply bidirectional level translation | Eliminates need for dual-rail translators or discrete resistor networks in mixed-voltage I/O interconnects |
| 5.0 V-tolerant inputs | Permits direct connection to 5 V legacy peripherals while powered from 1.8 V or 3.3 V rails |
| Reduced input thresholds (LVxT family) | Enables reliable recognition of 1.2 V/1.5 V/1.8 V inputs at higher VCC settings - critical for up-translation integrity |
| 3-state output with OE control | Supports bus sharing and multi-drop configurations without contention; OE pin has no internal pull-up |
| Industrial temperature range | Validated operation from –40°C to +125°C ensures reliability in uncontrolled thermal environments |
Applications
| Microcontroller I/O Expansion | Legacy Peripheral Interface |
|---|---|
Use Scenario: Interfacing a 1.8 V ARM Cortex-M0+ MCU GPIO to a 3.3 V SPI flash memory with shared data lines. IC Role / Device Role / Timing Role: Single-channel level translator buffering and enabling bidirectional signal flow on MISO/MOSI lines. Use Value: Eliminates external passive resistors or dedicated dual-supply translators, reducing BOM count and layout area while maintaining 50 MHz timing margins. |
Use Scenario: Connecting a modern 3.3 V SoC to a 5 V RS-232 transceiver IC requiring TTL-level inputs. IC Role / Device Role / Timing Role: Down-translating 3.3 V logic outputs to 5 V-compatible input thresholds without loading the SoC's GPIO. Use Value: Provides 5.0 V-tolerant input capability and rail-referenced 3.3 V output - avoids risk of overvoltage damage to the SoC. |
| Portable Device Power Sequencing | Industrial Sensor Hub Interface |
Use Scenario: Enabling/disabling communication lines between a battery-powered 2.5 V sensor and a 1.8 V application processor during sleep mode. IC Role / Device Role / Timing Role: 3-state buffer controlled by a power-management IC's enable signal to isolate domains during low-power states. Use Value: Prevents leakage current through inactive I/O paths; OE-controlled high-Z state reduces standby current to <1 µA per channel. |
Use Scenario: Bridging a 5 V analog front-end ADC and a 3.3 V FPGA control interface in a factory automation module. IC Role / Device Role / Timing Role: Unidirectional level translation for control signals (CS, WR, RD) operating at ≤25 MHz. Use Value: Guarantees VIH ≥1.37 V and VOL ≤0.2 V at 3.3 V VCC - meets FPGA input specs without margin loss across temperature. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar single-channel 3-state level translation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LV1T126DBVRG4 | Inverting buffer (A → Y̅); identical VCC range, drive strength, and translation capability | Required where signal polarity inversion is acceptable or needed in control logic | Select when functional inversion aligns with system timing or reset sequencing requirements |
| SN74LV1T34DBVRG4 | Non-inverting buffer without 3-state output; same LVxT input thresholds and VCC range | Used in fixed-direction, always-enabled signal paths where bus contention is not a concern | Choose when OE functionality is unnecessary and lower quiescent current (<0.5 µA) is prioritized |
Compared with SN74LV1T125DBVRG4, SN74LV1T126DBVRG4 offers identical performance with inverted logic, while SN74LV1T34DBVRG4 removes 3-state control to reduce complexity and static current - both require validation of signal polarity and bus architecture before substitution.
Availability
SN74LV1T125DBVRG4 is available at Aetrix Electronics and suitable for microcontroller I/O expansion, legacy peripheral interface, portable device power sequencing, and industrial sensor hub interface requiring stable component supply across automotive, industrial, and consumer electronics programs.
Supply support for SN74LV1T125DBVRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor company delivering analog and embedded processing solutions, with leadership in logic, power management, and signal chain technologies since 1930.
The SN74LV1T125DBVRG4 belongs to TI's LVxT family of single-gate logic devices engineered specifically for low-pin-count, single-supply voltage translation in space-constrained and mixed-voltage embedded systems.
FAQ
What is the maximum input voltage the SN74LV1T125DBVRG4 can tolerate?
The SN74LV1T125DBVRG4 supports input voltages up to 5.5 V regardless of VCC setting, making it safe for interfacing with 5 V signals even when powered from 1.8 V or 2.5 V. This 5 V tolerance applies only when the device is powered and operating within recommended conditions - absolute maximum rating is 7.0 V, but sustained operation above 5.5 V risks reliability degradation. The SN74LV1T125DBVRG4 input structure includes integrated negative clamp diodes to safely shunt excess voltage to VCC or GND.
Does the SN74LV1T125DBVRG4 require external pull-up or pull-down resistors on unused pins?
Yes - the SN74LV1T125DBVRG4 OE pin must never be left floating, as this can cause unintended output oscillation or increased power consumption. TI explicitly recommends tying OE to VCC (for always-enabled operation) or GND (to force high-Z) using a pull-up or pull-down resistor. For unused inputs, termination to VCC or GND is mandatory; a 10 kΩ resistor is recommended. The SN74LV1T125DBVRG4 has no internal pull resistors on any pin.
Can the SN74LV1T125DBVRG4 translate 1.2 V logic up to 3.3 V?
Yes - the SN74LV1T125DBVRG4 supports 1.2 V to 1.8 V up-translation when VCC = 1.8 V, and 1.8 V to 3.3 V up-translation when VCC = 3.3 V. Its LVxT input threshold design ensures VIH(MIN) drops to 0.99 V at 1.8 V VCC and 1.37 V at 3.3 V VCC, enabling reliable recognition of sub-2 V logic highs. The SN74LV1T125DBVRG4 does not support direct 1.2 V → 3.3 V translation in a single stage; two-stage cascading (e.g., 1.2 V → 1.8 V → 3.3 V) would be required.
What is the recommended bypass capacitor for the SN74LV1T125DBVRG4?
Texas Instruments specifies a 0.1 µF ceramic capacitor placed as close as possible (within 2 mm) to the VCC pin of the SN74LV1T125DBVRG4, with low-inductance connection to the local ground plane. This minimizes high-frequency supply noise and prevents output ringing during fast edge transitions. For systems with broad-spectrum noise, paralleling a 1 µF capacitor is acceptable - but the 0.1 µF unit remains mandatory. The SN74LV1T125DBVRG4 exhibits low ICC (<10 µA) but fast switching edges demand effective local decoupling to maintain signal integrity.
Is the SN74LV1T125DBVRG4 pin-compatible with other LV1T-series devices in SOT-23-5?
Yes - the SN74LV1T125DBVRG4 shares identical pinout (OE/A/GND/Y/VCC) and SOT-23-5 (DBV) package dimensions with all LV1T-series single-gate logic devices, including SN74LV1T00, SN74LV1T04, SN74LV1T34, and SN74LV1T126. This enables drop-in replacement for functional evaluation or design reuse, provided the logic function (buffer vs. inverter vs. NAND) and 3-state requirement match. The SN74LV1T125DBVRG4 marking "NEZ3" confirms DBV packaging and G4 finish compliance.
SN74LV1T125DBVRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LV
- Package/Case:
- SC-74A, SOT-753
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 1.6V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-5
SN74LV1T125DBVRG4 FAQ
1.How can I place an order for SN74LV1T125DBVRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LV1T125DBVRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LV1T125DBVRG4 reliable?
The price and inventory of SN74LV1T125DBVRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LV1T125DBVRG4 is usually 5 days.
3.What payment methods are accepted for SN74LV1T125DBVRG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LV1T125DBVRG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LV1T125DBVRG4?
SN74LV1T125DBVRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LV1T125DBVRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LV1T125DBVRG4?
For technical support, including SN74LV1T125DBVRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LV1T125DBVRG4 requirements.
6.How does Aetrix verify that SN74LV1T125DBVRG4 is sourced from the original manufacturer or authorized distributors?
All SN74LV1T125DBVRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LV1T125DBVRG4 meets industry standards.
7.What is the process for return or replacement of SN74LV1T125DBVRG4?
All SN74LV1T125DBVRG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74LV1T125DBVRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LV1T125DBVRG4 part is unused and in its original packaging.
Return procedure for SN74LV1T125DBVRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74LV1T125DBVRG4 Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

