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Home > Products > Integrated Circuits (ICs) > Logic > Buffers, Drivers, Receivers, Transceivers

Texas Instruments SN74LV1T126DBVRG4

Name: SN74LV1T126DBVRG4
Brand: Texas Instruments
SKU: SN74LV1T126DBVRG4
Price: 2.40 USD
Availability: InStock
Rating: 5 (2 reviews)

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Part No.:: SN74LV1T126DBVRG4

Manufacturer:: Texas Instruments

Category:: Buffers, Drivers, Receivers, Transceivers

Package:: SC-74A, SOT-753

Datasheet:: SN74LV1T126DBVRG4.pdf

Description:: IC BUF NON-INVERT 5.5V SOT23-5

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Product details

Overview

SN74LV1T126DBVRG4 from Texas Instruments is a single-supply CMOS buffer gate with 3-state output, designed for bidirectional logic-level translation between 1.2 V to 5.0 V domains. It supports up-translation (e.g., 1.8 V → 3.3 V at 3.3 V V_CC) and down-translation (e.g., 5.0 V → 3.3 V at 3.3 V V_CC), delivers ±8 mA drive at 5 V, operates from –40°C to 125°C, and features 5 V-tolerant inputs - used in voltage-domain bridging for portable SoC interfaces.

For engineers reviewing the SN74LV1T126DBVRG4 datasheet, SN74LV1T126DBVRG4 pinout, SN74LV1T126DBVRG4 application, or SN74LV1T126DBVRG4 equivalent, key selection criteria include verified 1.8–5.5 V supply range, confirmed 3-state control via active-high OE, measured 5.5 ns max propagation delay at 5 V/15 pF, and documented compatibility with AUP1G/LVC1G logic families.

Technical Context

The SN74LV1T126DBVRG4 implements LVxT-family enhanced input thresholds to enable reliable up-translation (e.g., 1.8 V input recognized as HIGH at 3.3 V V_CC) and 5 V-tolerant inputs for down-translation (e.g., 3.3 V input driving 2.5 V output at 2.5 V V_CC). Its output voltage is strictly referenced to V_CC, not input level.

It uses balanced CMOS push-pull outputs with symmetric sourcing/sinking capability (±8 mA at 5 V), supports DC–50 MHz operation at 3.3 V V_CC, and incorporates internal clamp diodes on all inputs and outputs per JESD17 latch-up spec (>250 mA).

Key Specifications

Parameter	Value and Actual Design Meaning
V_CC Range	1.8 V to 5.5 V - enables direct interface between mixed-voltage subsystems without external biasing.
Input Voltage Tolerance	5 V - allows connection to higher-voltage logic (e.g., 5 V MCU GPIO) while powered from 1.8 V or 2.5 V rails.
Output Drive	±8 mA at 5 V V_CC - sufficient to drive 50 Ω transmission lines or multiple LVC inputs without signal degradation.
Propagation Delay	5.5 ns max at 5 V/15 pF - supports clean 50 MHz digital signaling in timing-critical interconnect paths.
Operating Temperature	–40°C to +125°C - qualified for industrial and automotive under-hood applications requiring extended thermal margin.
Logic Output Reference	V_CC-referenced - ensures output HIGH = V_CC − 0.1 V, eliminating ambiguity when interfacing with downstream V_CC-based receivers.
ESD Rating (HBM)	±2000 V - meets IEC 61000-4-2 Level 2 requirements for board-level robustness in handheld and telecom equipment.

Pinout & Package

SOT-23 (DBV) 5-pin package: 2.90 mm × 2.80 mm footprint, 1.6 mm body width, 1.3 mm height, lead-free NiPdAu plating, MSL Level-1.

Pin/Terminal	Circuit Role	Design Meaning
1 - OE	Active-high output enable	Drives Y into high-impedance state when LOW; must not float - tie to V_CC or GND for static operation.
2 - A	Buffer input	5 V-tolerant; accepts 1.2 V–5.0 V logic levels; threshold adapts to V_CC (e.g., VIH = 0.99 V at 1.8 V V_CC).
3 - GND	Ground reference	Return path for all internal logic and output current; requires low-inductance connection to system ground plane.
4 - Y	3-state buffered output	CMOS-compatible output referenced to V_CC; sinks/sources up to 8 mA; high-Z state isolates downstream loads.
5 - V_CC	Positive supply	Single power rail defining output logic levels; bypass with 0.1 µF ceramic capacitor placed ≤2 mm from pin.

Key Features

Feature	Design Value
Single-supply level translation	Eliminates need for dual-rail translators or discrete resistor networks in mixed-voltage PCB designs.
5 V-tolerant inputs with reduced VIH/VIL	Enables reliable recognition of 1.2 V–3.3 V inputs across full 1.8–5.5 V V_CC range without external level-shifting circuitry.
3-state output with OE control	Allows bus sharing in multi-driver systems (e.g., shared debug interface or sensor data lines) without contention.
Industrial temperature range (–40°C to +125°C)	Supports deployment in automotive infotainment, industrial PLC I/O modules, and base station RF front-end control.
Low ICC (≤10 µA typical)	Reduces quiescent power in always-on subsystems such as battery-backed real-time clocks or wake-on-event logic.

Applications

Portable SoC Interface	Server Baseboard Management
Use Scenario: Interfacing a 1.8 V application processor GPIO to a 3.3 V PMIC enable line in a smartphone or tablet. IC Role / Device Role / Timing Role: Single-direction level translator buffering control signals between voltage domains with precise timing alignment. Use Value: Eliminates risk of overvoltage damage to the 1.8 V processor while ensuring fast, glitch-free enable assertion to the 3.3 V PMIC.	Use Scenario: Isolating 5 V legacy BMC reset signals from 2.5 V FPGA configuration logic in a rack server motherboard. IC Role / Device Role / Timing Role: 3-state buffer enabling dynamic control of reset propagation during FPGA reconfiguration sequences. Use Value: Prevents unintended resets during hot-swap events by asserting high-Z state on BMC-initiated reset lines when FPGA is in programming mode.
Automotive ADAS Sensor Hub	Industrial PLC Digital I/O Module
Use Scenario: Translating 3.3 V camera sensor sync pulses to 5 V microcontroller timer capture inputs in an automotive surround-view system. IC Role / Device Role / Timing Role: Low-skew buffer with sub-6 ns propagation delay preserving edge integrity for time-of-flight synchronization. Use Value: Maintains <±1 ns jitter budget required for pixel-accurate image stitching across four camera channels.	Use Scenario: Level-shifting 24 V optocoupler-isolated field inputs to 3.3 V ARM Cortex-M4 GPIO in a programmable logic controller. IC Role / Device Role / Timing Role: Input-side translator converting industrial 24 V logic to safe 3.3 V domain for microcontroller sampling. Use Value: Enables direct connection to isolated input stages without additional voltage dividers or Schmitt triggers, reducing BOM count and layout area.

Portable SoC Interface

Server Baseboard Management

Use Scenario: Interfacing a 1.8 V application processor GPIO to a 3.3 V PMIC enable line in a smartphone or tablet.

IC Role / Device Role / Timing Role: Single-direction level translator buffering control signals between voltage domains with precise timing alignment.

Use Value: Eliminates risk of overvoltage damage to the 1.8 V processor while ensuring fast, glitch-free enable assertion to the 3.3 V PMIC.

Use Scenario: Isolating 5 V legacy BMC reset signals from 2.5 V FPGA configuration logic in a rack server motherboard.

IC Role / Device Role / Timing Role: 3-state buffer enabling dynamic control of reset propagation during FPGA reconfiguration sequences.

Use Value: Prevents unintended resets during hot-swap events by asserting high-Z state on BMC-initiated reset lines when FPGA is in programming mode.

Automotive ADAS Sensor Hub

Industrial PLC Digital I/O Module

Use Scenario: Translating 3.3 V camera sensor sync pulses to 5 V microcontroller timer capture inputs in an automotive surround-view system.

IC Role / Device Role / Timing Role: Low-skew buffer with sub-6 ns propagation delay preserving edge integrity for time-of-flight synchronization.

Use Value: Maintains <±1 ns jitter budget required for pixel-accurate image stitching across four camera channels.

Use Scenario: Level-shifting 24 V optocoupler-isolated field inputs to 3.3 V ARM Cortex-M4 GPIO in a programmable logic controller.

IC Role / Device Role / Timing Role: Input-side translator converting industrial 24 V logic to safe 3.3 V domain for microcontroller sampling.

Use Value: Enables direct connection to isolated input stages without additional voltage dividers or Schmitt triggers, reducing BOM count and layout area.

Equivalent & Alternatives

The following parts are listed as comparable options for similar logic-level translation applications.

Alternative Part	Technical Difference	Application Difference	Selection Advice
SN74LV1T125DBVRG4	Same SOT-23-5 package and V_CC range, but active-low OE instead of active-high.	Requires inverted enable logic in host firmware or upstream gate; identical translation performance otherwise.	Select when existing design already uses active-low control signals to minimize PCB changes.
TXS0101DCKR	Auto-direction sensing, no OE pin; lower drive (±2 mA), higher ICC (20 µA typical), supports 1.65–5.5 V.	Eliminates OE routing but adds direction-detection latency; unsuitable for synchronous clock forwarding or deterministic timing paths.	Prefer for simple data lines where direction is predictable and timing margin is >10 ns; avoid for clock or reset distribution.

Compared with SN74LV1T126DBVRG4, SN74LV1T125DBVRG4 offers pin-compatible replacement with only OE polarity change, while TXS0101DCKR trades deterministic 3-state control for automatic direction detection - making it less suitable for timing-critical or bidirectional bus arbitration scenarios.

Availability

SN74LV1T126DBVRG4 is available at Aetrix Electronics and suitable for portable SoC interfaces, server baseboard management, automotive ADAS sensor hubs, and industrial PLC digital I/O modules requiring stable component supply across extended temperature ranges.

Supply support for SN74LV1T126DBVRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor company specializing in analog and embedded processing technologies, with leadership in precision analog, power management, and logic solutions for industrial, automotive, and communications markets.

The SN74LV1T126DBVRG4 belongs to TI's LVxT family of single-gate logic devices engineered specifically for low-pin-count, single-supply voltage translation in space-constrained, mixed-voltage embedded systems.

FAQ

What is the maximum operating frequency supported by the SN74LV1T126DBVRG4?

The SN74LV1T126DBVRG4 is characterized up to 50 MHz at 3.3 V V_CC with 15 pF load, delivering 7.0 ns typical propagation delay. At 5 V V_CC, it supports DC–50 MHz operation with 5.5 ns max t_pd. Performance degrades at lower V_CC: 15 MHz max at 1.8 V due to increased delay (14.0 ns max). Always verify timing margins against actual load and trace capacitance in final layout.

Can the SN74LV1T126DBVRG4 translate 5 V inputs while powered from 1.8 V?

Yes - the SN74LV1T126DBVRG4 has 5 V-tolerant inputs and supports down-translation from 5.0 V to 1.8 V output when V_CC = 1.8 V. Input thresholds adapt to V_CC (VIH ≈ 0.99 V, VIL ≈ 0.55 V), and the output will swing between 0 V and ~1.7 V. This is validated per datasheet Section 1.1 "Down translation" and Table 6.5 electrical characteristics.

Is the SN74LV1T126DBVRG4 pin-compatible with other LV1T-series devices in SOT-23-5?

Yes - the SN74LV1T126DBVRG4 shares identical SOT-23-5 (DBV) pinout with SN74LV1T00, SN74LV1T04, SN74LV1T125, and other LV1Txx devices in DBV package. Pin 1 = OE (or /OE), Pin 2 = A (input), Pin 3 = GND, Pin 4 = Y (output), Pin 5 = V_CC. This enables drop-in substitution within same function group, subject to OE polarity and logic type.

Does the SN74LV1T126DBVRG4 require external pull-up or pull-down resistors on unused pins?

Yes - all unused inputs, including OE, must be terminated to V_CC or GND per TI's SCBA004 guidance. Floating OE causes undefined output states and potential oscillation. For SN74LV1T126DBVRG4, tie OE to V_CC for always-enabled operation or to GND for permanently disabled (high-Z) output. No pull resistors needed on Y or A if actively driven.

What is the thermal resistance (RθJA) of the SN74LV1T126DBVRG4 in its SOT-23 package?

The SN74LV1T126DBVRG4 in DBV (SOT-23) package has RθJA = 278°C/W, per TI's SCLS744D revision FEBRUARY 2024 datasheet Section 6.4. This value assumes standard JEDEC 2-layer board conditions. Actual junction temperature rise depends on PCB copper area, airflow, and power dissipation - max ICC is 10 µA, so self-heating is negligible under static conditions.

SN74LV1T126DBVRG4 Specifications

Product attributes: Attribute value

Manufacturer:: Texas Instruments

Series:: 74LV

Package/Case:: SC-74A, SOT-753

Packaging:: Tape & Reel (TR)

Product Status:: Discontinued at Digi-Key

Logic Type:: Buffer, Non-Inverting

Number of Elements:: 1

Number of Bits per Element:: 1

Input Type:: -

Output Type:: 3-State

Current - Output High, Low:: 8mA, 8mA

Voltage - Supply:: 1.6V ~ 5.5V

Operating Temperature:: -40°C ~ 125°C (TA)

Grade:: -

Qualification:: -

Mounting Type:: Surface Mount

Supplier Device Package:: SOT-23-5

SN74LV1T126DBVRG4 FAQ

1.How can I place an order for SN74LV1T126DBVRG4 through Aetrix?

Please submit a Request for Quotation (RFQ) for SN74LV1T126DBVRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.

2.Are the price and stock information for SN74LV1T126DBVRG4 reliable?

The price and inventory of SN74LV1T126DBVRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LV1T126DBVRG4 is usually 5 days.

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Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.

5.How can I obtain technical support or documentation for SN74LV1T126DBVRG4?

For technical support, including SN74LV1T126DBVRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LV1T126DBVRG4 requirements.

6.How does Aetrix verify that SN74LV1T126DBVRG4 is sourced from the original manufacturer or authorized distributors?

All SN74LV1T126DBVRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LV1T126DBVRG4 meets industry standards.

7.What is the process for return or replacement of SN74LV1T126DBVRG4?

All SN74LV1T126DBVRG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74LV1T126DBVRG4, returns or replacements are accepted under the following conditions:

1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.

2.The issue is reported within 90 days of delivery.

3.The SN74LV1T126DBVRG4 part is unused and in its original packaging.

Return procedure for SN74LV1T126DBVRG4:

1.Submit a request within 90 days.

2.Obtain a Return Material Authorization (RMA) from Aetrix.

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