Texas Instruments SN74LV1T126DCKRG4
- Part No.:
- SN74LV1T126DCKRG4
- Manufacturer:
- Texas Instruments
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
SN74LV1T126DCKRG4.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V SC70-5
- Quantity:
- Payment:

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Product details
Overview
SN74LV1T126DCKRG4 from Texas Instruments is a single-supply CMOS buffer gate with 3-state output, designed for bidirectional logic-level translation between 1.2 V and 5.0 V domains. It operates across 1.8 V–5.5 V VCC, delivers up to 8 mA output drive at 5 V, supports 50 MHz switching at 3.3 V, and features 5 V-tolerant inputs - enabling use in mixed-voltage I/O interfacing between microcontrollers and legacy peripherals in portable and telecom systems.
For engineers reviewing the SN74LV1T126DCKRG4 datasheet, SN74LV1T126DCKRG4 pinout, SN74LV1T126DCKRG4 application, or SN74LV1T126DCKRG4 equivalent, key selection criteria include its 3-state enable control, voltage-agnostic input thresholds (e.g., VIH = 0.99 V at 1.8 V VCC), rail-referenced CMOS output, and SC70-5 package compatibility with space-constrained PCB layouts.
Technical Context
The SN74LV1T126DCKRG4 implements an LVxT-family enhanced-input architecture with reduced VIH/VIL thresholds to enable reliable up-translation (e.g., 1.2 V → 1.8 V at 1.8 V VCC) and down-translation (e.g., 5.0 V → 3.3 V at 3.3 V VCC). Its output voltage is strictly referenced to VCC, ensuring consistent logic levels regardless of input voltage domain.
It integrates balanced CMOS push-pull outputs with 8 mA sink/source capability at 5 V, 7 mA at 3.3 V, and 3 mA at 1.8 V - sufficient to drive moderate capacitive loads while minimizing signal integrity issues. The device supports operation from –40°C to +125°C and exhibits latch-up immunity exceeding 250 mA per JESD17.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.8 V to 5.5 V - enables direct integration into 1.8 V, 2.5 V, 3.3 V, and 5 V systems without external level-shifting circuitry. |
| Input Voltage Tolerance | 5 V tolerant on all inputs - allows safe connection to higher-voltage signal sources (e.g., 5 V MCU GPIO) when VCC = 1.8 V or 2.5 V. |
| Output Drive | 8 mA at 5 V VCC - provides robust edge rates and noise margin for driving 15 pF loads with ≤6.5 ns propagation delay. |
| Max Switching Frequency | 50 MHz at 3.3 V VCC - supports high-speed serial control lines (e.g., SPI clock, I²C SCL) in embedded interfaces. |
| Operating Temperature | –40°C to +125°C - qualified for industrial and automotive under-hood applications requiring extended thermal reliability. |
| Propagation Delay | 4.0 ns (typ) at 3.3 V, 15 pF - ensures timing predictability in synchronous digital interconnects with tight setup/hold windows. |
| 3-State Enable Timing | tPZH/tPLZ = 4.5 ns (typ) at 3.3 V - enables fast bus arbitration and dynamic I/O sharing in multi-master systems. |
Pinout & Package
SN74LV1T126DCKRG4 is packaged in a 5-pin SC70 (DCK) case measuring 2.00 mm × 2.10 mm (body: 2.00 mm × 1.25 mm), optimized for ultra-compact PCB layouts in portable electronics.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| OE (Pin 1) | Active-high output enable | Drives Y to high-impedance state when low; must not be left floating - tie to VCC or GND via pull-up/down resistor if unused. |
| A (Pin 2) | Non-inverting data input | Accepts 1.2 V–5.5 V logic signals; VIH/VIL thresholds scale with VCC to support both up- and down-translation modes. |
| GND (Pin 3) | Ground reference | Return path for all internal logic and output current; requires low-inductance connection to system ground plane. |
| Y (Pin 4) | 3-state buffered output | CMOS-compatible output referenced to VCC; drives high/low or enters high-Z when OE = L - ideal for shared bus architectures. |
| VCC (Pin 5) | Positive supply | Defines output logic levels and input thresholds; requires local 0.1 µF ceramic bypass capacitor placed adjacent to pin. |
Key Features
| Feature | Design Value |
|---|---|
| Bidirectional level translation | Supports verified up-translation (1.2 V → 1.8 V) and down-translation (5.0 V → 3.3 V) without external components or direction control. |
| Rail-referenced CMOS output | VOH ≥ VCC – 0.1 V and VOL ≤ 0.35 V ensure full logic swing compatibility with AUP1G/LVC1G families and standard CMOS loads. |
| 5 V-tolerant inputs | Enables direct interface to 5 V systems (e.g., legacy sensors, industrial PLCs) while operating from 1.8 V or 2.5 V rails - eliminating discrete resistive dividers. |
| Industrial temperature range | –40°C to +125°C operation validated per JEDEC JESD22-A104 - suitable for deployment in harsh environments without derating. |
| Low static power | ICC ≤ 10 µA across full VCC range - critical for battery-powered devices where quiescent current directly impacts runtime. |
Applications
| Industrial Sensor Interface | Portable Device Power Management |
|---|---|
Use Scenario: Interfacing a 5 V analog sensor output to a 1.8 V microcontroller ADC input with precise timing control. IC Role / Device Role / Timing Role: Level translator and signal conditioner that converts 5 V sensor logic to 1.8 V–compatible levels while preserving signal integrity. Use Value: Eliminates need for external voltage dividers or dedicated level-shifters, reducing BOM count and board area by >30% in compact sensor modules. |
Use Scenario: Enabling/disabling power-rail monitoring signals between a 3.3 V PMIC and 1.2 V SoC during sleep/wake transitions. IC Role / Device Role / Timing Role: 3-state buffer providing controlled isolation and fast enable/disable timing (tPZH ≤ 4.5 ns) for dynamic power sequencing. Use Value: Ensures glitch-free power-state handshaking with sub-10 ns timing margins, preventing false wake-ups or brown-out detection errors. |
| Telecom Baseband I/O Expansion | Automotive Infotainment Serial Bus |
Use Scenario: Extending I²C or SPI bus lines between a 3.3 V baseband processor and multiple 1.8 V peripheral ICs in LTE/5G radio modules. IC Role / Device Role / Timing Role: Bidirectional level-shifting repeater supporting 50 MHz clock rates and 15 pF load capacitance per segment. Use Value: Maintains signal fidelity across long traces (>5 cm) while meeting I²C timing budgets (tBUF, tHD:STA) without added termination or buffering stages. |
Use Scenario: Isolating CAN transceiver status pins (5 V tolerant) from a 2.5 V automotive microcontroller's GPIO bank during ECU diagnostics. IC Role / Device Role / Timing Role: 3-state isolator with 5 V-tolerant input and rail-aligned output, enabling safe hot-plug detection and fault signaling. Use Value: Prevents damage from transient overvoltage events on diagnostic lines while maintaining <100 ns response latency for real-time fault reporting. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar logic-level translation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LV1T125DCKRG4 | Same SC70-5 package and VCC range, but non-inverting buffer with 3-state output and identical VIH/VIL thresholds - lacks up-translation support below 1.8 V input. | Not suitable for 1.2 V → 1.8 V up-translation; limited to 1.8 V+ input domains. | Select SN74LV1T125DCKRG4 only when input signals are ≥1.8 V and no sub-1.8 V translation is required. |
| TXS0102DCUR | 2-channel auto-direction-sensing translator in VSSOP-8; supports 1.2 V–3.3 V bidirectional translation but requires no OE control and has higher ICC (20 µA). | Designed for I²C/SMBus; unsuitable for unidirectional buffered control signals requiring explicit 3-state control. | Choose TXS0102DCUR for open-drain bus applications; avoid for push-pull GPIO expansion where OE-driven bus arbitration is needed. |
Compared with SN74LV1T125DCKRG4 and TXS0102DCUR, the SN74LV1T126DCKRG4 uniquely combines single-channel 3-state control, 5 V-tolerant inputs, and verified 1.2 V up-translation - making it the only option among the three capable of interfacing sub-1.8 V logic (e.g., LPDDR I/O) to higher-voltage domains without external biasing.
Availability
SN74LV1T126DCKRG4 is available at Aetrix Electronics and suitable for industrial sensor interfaces, portable power management subsystems, telecom baseband I/O expansion, and automotive infotainment serial buses requiring stable component supply across extended temperature ranges.
Supply support for SN74LV1T126DCKRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 90 years of innovation in power management, signal chain, and interface technologies.
The SN74LV1T126DCKRG4 belongs to TI's LVxT family of single-gate logic devices engineered specifically for voltage-domain bridging in space- and power-constrained systems - targeting portable, telecom, and industrial applications where mixed-voltage interoperability is critical.
FAQ
What is the maximum input voltage the SN74LV1T126DCKRG4 can tolerate?
The SN74LV1T126DCKRG4 features 5 V-tolerant inputs, meaning it safely accepts input voltages up to 5.5 V regardless of VCC level - verified per Absolute Maximum Ratings. This allows direct connection to 5 V signal sources (e.g., legacy microcontrollers) even when operating from 1.8 V or 2.5 V supply rails, eliminating external protection circuitry.
Does the SN74LV1T126DCKRG4 support bidirectional level translation?
No - the SN74LV1T126DCKRG4 is a unidirectional buffer: input A drives output Y, with direction fixed by pin assignment. However, it supports bidirectional *voltage translation* (up and down) because its input thresholds adapt to VCC, allowing 1.2 V signals to drive a 1.8 V output or 5 V signals to produce a 3.3 V output - all within a single direction of data flow.
What is the recommended bypass capacitor for the SN74LV1T126DCKRG4 VCC pin?
A 0.1 µF ceramic capacitor is recommended for the SN74LV1T126DCKRG4 VCC pin, placed as close as possible to the pin with minimal trace length. For improved high-frequency noise suppression, TI recommends paralleling this with a 1 µF capacitor - both must connect directly to the local ground plane to maintain signal integrity and prevent supply bounce during output switching.
Can the SN74LV1T126DCKRG4 operate at 1.6 V VCC?
No - the SN74LV1T126DCKRG4 has a minimum recommended VCC of 1.8 V per Section 6.3 of the datasheet. While absolute maximum ratings permit VCC down to –0.5 V, functional operation is only guaranteed from 1.8 V to 5.5 V. At 1.6 V, VIH/VIL thresholds become undefined, and output drive falls outside specification - risking logic misinterpretation or failure to drive downstream loads.
How does the OE pin function on the SN74LV1T126DCKRG4?
The OE (Output Enable) pin on the SN74LV1T126DCKRG4 is active-high: when high, output Y follows input A; when low, Y enters high-impedance state. TI explicitly warns against leaving OE floating due to risk of oscillation - it must be tied to VCC (for always-enabled mode) or GND (for always-disabled mode), or driven by a clean logic signal with defined slew rate.
SN74LV1T126DCKRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LV
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 1.6V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-70-5
SN74LV1T126DCKRG4 FAQ
1.How can I place an order for SN74LV1T126DCKRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LV1T126DCKRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LV1T126DCKRG4 reliable?
The price and inventory of SN74LV1T126DCKRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LV1T126DCKRG4 is usually 5 days.
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5.How can I obtain technical support or documentation for SN74LV1T126DCKRG4?
For technical support, including SN74LV1T126DCKRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LV1T126DCKRG4 requirements.
6.How does Aetrix verify that SN74LV1T126DCKRG4 is sourced from the original manufacturer or authorized distributors?
All SN74LV1T126DCKRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LV1T126DCKRG4 meets industry standards.
7.What is the process for return or replacement of SN74LV1T126DCKRG4?
All SN74LV1T126DCKRG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74LV1T126DCKRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LV1T126DCKRG4 part is unused and in its original packaging.
Return procedure for SN74LV1T126DCKRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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