Texas Instruments SN74LV1T126QDBVRQ1
- Part No.:
- SN74LV1T126QDBVRQ1
- Manufacturer:
- Texas Instruments
- Package:
- SC-74A, SOT-753
- Datasheet:
-
SN74LV1T126QDBVRQ1.pdf
- Description:
- SN74LV1T126QDBVRQ1
- Quantity:
- Payment:

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Product details
Overview
SN74LV1T126QDBVRQ1 from Texas Instruments is an automotive-grade single-buffer gate with 3-state output and integrated voltage translation, performing Y = A logic in positive polarity. It operates from 1.8 V to 5.5 V, supports bidirectional level translation (e.g., 1.2 V → 1.8 V up-translation and 5.0 V → 3.3 V down-translation), tolerates 5.5-V inputs, and delivers ≤4.7 ns propagation delay at 5-V VCC. It is used in automotive body control modules for enabling/disabling sensor data paths between mixed-voltage subsystems.
For engineers reviewing the SN74LV1T126QDBVRQ1 datasheet, SN74LV1T126QDBVRQ1 pinout, SN74LV1T126QDBVRQ1 application, or SN74LV1T126QDBVRQ1 equivalent, key selection criteria include AEC-Q100 Grade 1 qualification (-40°C to +125°C), 5.5-V tolerant inputs, 3-state output control via OE, and verified up/down translation across 1.2–5.0 V domains without external components.
Technical Context
This device implements a single CMOS buffer with active-high 3-state enable (OE) and LVxT-enhanced input thresholds enabling true bidirectional voltage translation. Its input stage uses reduced VIH/VIL thresholds (e.g., VIH = 1.1 V min at 1.65–2.0 V VCC) to accept sub-supply logic levels, while its 5.5-V tolerant pins allow higher-voltage signals to drive it directly under down-translation conditions.
The output is referenced solely to VCC and drives CMOS-compatible levels (VOH ≥ VCC − 0.1 V, VOL ≤ 0.25 V at 3.3 V), with balanced sourcing/sinking capability (±15 mA at 3.3 V). Propagation delay scales inversely with VCC: 4.7 ns max at 5.0 V, 7.3 ns max at 3.3 V, and 14.9 ns max at 1.8 V - all specified over full automotive temperature range.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.8 V to 5.5 V - enables direct interface between 1.2-V, 1.8-V, 2.5-V, 3.3-V, and 5-V logic domains without external biasing. |
| Input Voltage Tolerance | Up to 5.5 V - allows connection to higher-voltage buses (e.g., 5-V microcontroller GPIO) while powered from lower VCC (e.g., 3.3 V or 1.8 V). |
| Propagation Delay (TPD) | ≤4.7 ns at 5.0-V VCC, CL = 15 pF - supports signal integrity in high-speed automotive serial links up to 150 Mbps. |
| Output Drive Strength | ±15 mA at 3.3-V VCC - sufficient to drive multiple standard CMOS loads or moderate PCB trace capacitance without buffering. |
| AEC-Q100 Grade | Grade 1 (−40°C to +125°C ambient) - qualified for engine bay, transmission control, and ADAS domain controller applications. |
| ESD Rating | HBM ±2000 V, CDM ±1000 V - meets automotive robustness requirements for assembly and field operation. |
| Quiescent Current (ICC) | ≤10 µA at 1.8–5.5 V - enables low-power always-on monitoring circuits in battery-sensitive systems. |
Pinout & Package
SOT-23-5 (DBV) package: 2.9 mm × 2.8 mm footprint, 2.9 mm × 1.6 mm body, 1.45 mm height, lead pitch 0.95 mm. RoHS-compliant, Pb-free, matte tin lead finish.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 - OE | Active-high output enable | Drives output Y to high-impedance when LOW; must be tied HIGH or controlled by system MCU GPIO to activate buffer function. |
| 2 - A | Buffer input | Accepts logic levels from 1.2 V to 5.5 V; threshold adapts to VCC (e.g., VIH = 1.1 V min at 1.8 V VCC). |
| 3 - GND | Power ground reference | Return path for all internal logic and output current; requires low-inductance connection to system ground plane. |
| 4 - Y | 3-state buffered output | Drives VCC-referenced CMOS levels; high-impedance state isolates downstream circuitry during OE = LOW. |
| 5 - VCC | Supply voltage input | Defines output voltage swing and input threshold levels; bypass capacitor (0.1 µF ceramic) required within 5 mm. |
Key Features
| Feature | Design Value |
|---|---|
| Integrated voltage translation | Eliminates need for discrete resistor dividers or dedicated translators - supports 1.2→1.8 V, 1.8→3.3 V, 5.0→3.3 V, and other combinations in one chip. |
| 5.5-V tolerant inputs | Enables direct connection to legacy 5-V peripherals (e.g., LIN transceivers, legacy sensors) while operating from modern 3.3-V or 1.8-V rails. |
| Automotive qualification | AEC-Q100 Grade 1, HBM ±2 kV, CDM ±1 kV - validated for under-hood and safety-critical ECUs without derating. |
| Low dynamic power | CPD = 14 pF at 5.5 V - limits switching power to <1 mW at 10 MHz with 15-pF load, critical for thermally constrained modules. |
| Fast enable/disable timing | TEN ≤ 14 ns, TDIS ≤ 14.3 ns at 3.3 V - ensures clean signal gating in time-critical diagnostics and bus arbitration sequences. |
Applications
| Body Control Module Signal Gating | ADAS Camera Interface Level Shifting |
|---|---|
|
Use Scenario: Isolating CAN/LIN diagnostic lines during ECU sleep mode to prevent bus contention and leakage. IC Role / Device Role / Timing Role: Single-buffer gate with 3-state output controlled by MCU's wake-up controller; OE driven LOW to disconnect sensor data path. Use Value: Enables zero-current isolation of 5-V LIN bus from 3.3-V microcontroller I/O while maintaining AEC-Q100 compliance and eliminating external MOSFET switches. |
Use Scenario: Translating 1.8-V MIPI CSI-2 clock/data from image sensor to 3.3-V SoC video processor in rear-view camera module. IC Role / Device Role / Timing Role: Up-translator buffer converting 1.8-V sensor outputs to 3.3-V logic levels compatible with SoC input thresholds. Use Value: Achieves sub-8 ns propagation delay at 3.3 V, preserving signal integrity for 150 Mbps pixel streams without added jitter or skew. |
| Engine Control Unit I/O Expansion | Electric Power Steering (EPS) Motor Driver Interface |
|
Use Scenario: Adding isolated GPIOs to legacy 5-V ECU microcontroller for controlling new 1.8-V status LEDs and fault indicators. IC Role / Device Role / Timing Role: Down-translator buffer accepting 5-V MCU outputs and driving 1.8-V LED drivers with precise VOH/VOL matching. Use Value: Eliminates need for dual-supply level shifters; supports 5-V input tolerance and 1.8-V output swing with <0.25 V VOL at 3 mA sink. |
Use Scenario: Enabling/disabling PWM signals sent from 3.3-V motor controller to 5-V gate driver ICs in EPS actuator. IC Role / Device Role / Timing Role: 3-state buffer placed between controller and driver inputs; OE synchronized with safety watchdog to force Hi-Z on fault. Use Value: Provides fail-safe signal isolation with <15 ns enable/disable latency, meeting ISO 26262 ASIL-B functional safety timing constraints. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar single-buffer translation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1T45DBVR | Direction-controlled dual-supply translator (A/B ports); no 3-state output; requires separate VCCA/VCCB rails. | Requires two independent supplies; unsuitable for single-rail 3-state gating use cases like bus isolation. | Choose only if bidirectional translation with independent voltage domains is required; not a drop-in replacement for OE-controlled unidirectional buffering. |
| MC74VHC1GT126DTT1G | Non-automotive grade; AEC-Q100 not qualified; VIH/VIL thresholds fixed for 3.3/5-V operation only; no 1.2-V or 1.8-V up-translation support. | Limited to commercial temperature range (−40°C to +85°C); lacks 5.5-V input tolerance and LVxT enhanced thresholds. | Select only for non-automotive industrial applications where AEC-Q100 and wide-voltage translation are unnecessary. |
Compared with SN74LV1T126QDBVRQ1, SN74LVC1T45DBVR adds direction control but removes 3-state gating and automotive qualification, while MC74VHC1GT126DTT1G offers lower cost but sacrifices AEC-Q100 compliance, 5.5-V tolerance, and sub-2-V up-translation capability - making SN74LV1T126QDBVRQ1 uniquely suited for safety-critical, multi-voltage automotive signal routing.
Availability
SN74LV1T126QDBVRQ1 is available at Aetrix Electronics and suitable for automotive body control modules, ADAS camera interfaces, engine control units, and electric power steering systems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SN74LV1T126QDBVRQ1 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and automotive ICs, with decades of experience in high-reliability automotive electronics design and manufacturing.
SN74LV1T126QDBVRQ1 belongs to TI's LVxT family of single-gate logic devices engineered specifically for voltage translation in space-constrained automotive ECUs, where minimizing bill-of-materials and board area while meeting AEC-Q100 Grade 1 is essential.
FAQ
What is the maximum input voltage the SN74LV1T126QDBVRQ1 can tolerate?
The SN74LV1T126QDBVRQ1 supports 5.5-V tolerant inputs across all operating conditions. This means input signals up to 5.5 V may be applied regardless of VCC level - enabling direct interfacing with 5-V microcontrollers or sensors while the device is powered from 1.8 V, 2.5 V, or 3.3 V. Exceeding 5.5 V risks permanent damage per Absolute Maximum Ratings.
Does the SN74LV1T126QDBVRQ1 support both up-translation and down-translation?
Yes, the SN74LV1T126QDBVRQ1 supports verified up-translation (e.g., 1.2 V → 1.8 V, 1.8 V → 3.3 V) and down-translation (e.g., 5.0 V → 3.3 V, 3.3 V → 1.8 V) as defined in its LVxT architecture. Translation direction is determined solely by VCC selection and input signal levels - no external components or configuration pins are needed.
What is the operating temperature range for the SN74LV1T126QDBVRQ1?
The SN74LV1T126QDBVRQ1 is qualified to AEC-Q100 Grade 1, supporting continuous operation from −40°C to +125°C ambient temperature. This rating covers under-hood, transmission, and chassis-mounted applications where junction temperatures may exceed 105°C, and thermal derating is not required within this range.
Can the SN74LV1T126QDBVRQ1 drive a 50-pF capacitive load reliably?
Yes - the SN74LV1T126QDBVRQ1 is fully characterized for CL = 50 pF across all VCC and temperature conditions. At 3.3-V VCC, propagation delay remains ≤8.8 ns and output drive strength maintains ±15 mA, ensuring signal integrity in typical automotive PCB environments with moderate trace capacitance and stub loading.
Is the SN74LV1T126QDBVRQ1 pin-compatible with other TI single-gate buffers?
No - the SN74LV1T126QDBVRQ1 uses a unique 5-pin SOT-23 (DBV) pinout optimized for OE/A/GND/Y/VCC. It is not pin-compatible with SN74LVC1G125, SN74AUP1G07, or SN74LV1T34. Layout reuse requires verification against the exact DBV mechanical drawing and thermal pad recommendations in TI's SCLS926A datasheet.
SN74LV1T126QDBVRQ1 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LV
- Package/Case:
- SC-74A, SOT-753
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 8mA, 8mA
- Voltage - Supply:
- 1.6V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- Automotive
- Qualification:
- AEC-Q100
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SOT-23-5
SN74LV1T126QDBVRQ1 FAQ
1.How can I place an order for SN74LV1T126QDBVRQ1 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LV1T126QDBVRQ1 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LV1T126QDBVRQ1 reliable?
The price and inventory of SN74LV1T126QDBVRQ1 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LV1T126QDBVRQ1 is usually 5 days.
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5.How can I obtain technical support or documentation for SN74LV1T126QDBVRQ1?
For technical support, including SN74LV1T126QDBVRQ1 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LV1T126QDBVRQ1 requirements.
6.How does Aetrix verify that SN74LV1T126QDBVRQ1 is sourced from the original manufacturer or authorized distributors?
All SN74LV1T126QDBVRQ1 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LV1T126QDBVRQ1 meets industry standards.
7.What is the process for return or replacement of SN74LV1T126QDBVRQ1?
All SN74LV1T126QDBVRQ1 units undergo pre-shipment inspection (PSI). If there is an issue with SN74LV1T126QDBVRQ1, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LV1T126QDBVRQ1 part is unused and in its original packaging.
Return procedure for SN74LV1T126QDBVRQ1:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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