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Texas Instruments SN74LV367ADGVR
- Part No.:
- SN74LV367ADGVR
- Manufacturer:
- Texas Instruments
- Package:
- 16-TFSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74LV367ADGVR.pdf
- Description:
- IC BUF NON-INVERT 5.5V 16TVSOP
- Quantity:
- Payment:
- Shipping:
Inventory:1,543
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Product details
Overview
SN74LV367ADGVR from Texas Instruments is a hex noninverting buffer/line driver with 3-state outputs, designed for 2 V to 5.5 V operation. It features dual output-enable controls (1OE, 2OE), 7 ns max propagation delay at 5 V, ±8 mA output drive at 3 V, and 5.5 V-tolerant inputs - enabling mixed-voltage interfacing in bus expansion and display driver applications.
For engineers reviewing the SN74LV367ADGVR datasheet, SN74LV367ADGVR pinout, SN74LV367ADGVR application, or SN74LV367ADGVR equivalent, this page delivers verified functional role, TVSOP-16 package mapping, real-world timing and drive specs, and two validated alternative parts for bus interface and LED matrix designs.
Technical Context
The SN74LV367ADGVR implements six independent noninverting buffers grouped as two functional blocks (1A1–1Y3 + 1A4 & 2Y1–2Y2), each controlled by its own active-low output-enable input (1OE, 2OE). Its balanced CMOS 3-state outputs support bidirectional bus driving with matched sink/source capability up to ±8 mA at 3 V.
It supports mixed-mode voltage operation: inputs tolerate up to 5.5 V regardless of VCC (2–5.5 V), enabling level translation from higher-voltage logic to lower-VCC systems. The device includes partial power-down (Ioff) protection and meets JESD17 latch-up immunity (>250 mA).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2 V to 5.5 V - enables interoperability across 2.5 V, 3.3 V, and 5 V logic domains without level shifters. |
| tpd (max) | 7 ns at VCC = 5 V, CL = 15 pF - ensures sub-10 ns timing margin for high-speed address/data bus buffering. |
| IOL / IOH | ±8 mA at VCC = 3 V - sufficient to directly drive LEDs or terminate 50 Ω transmission lines with controlled edge rates. |
| Input Voltage Tolerance | Up to 5.5 V on all inputs - allows safe down-translation from 5 V microcontrollers to 3.3 V or 2.5 V system buses. |
| 3-State Leakage (IOZ) | ±5 µA at VCC = 5.5 V - minimizes bus contention current when outputs are disabled in shared-bus configurations. |
| ESD Rating (HBM) | ±2000 V - exceeds JEDEC JS-001 requirements for robust handling in automated assembly and field environments. |
| Operating Temperature | –40°C to +85°C - qualified for industrial-grade embedded control and display subsystems. |
Pinout & Package
SN74LV367ADGVR is packaged in a 16-pin TVSOP (DGV) with 0.5 mm pitch, body size 3.60 mm × 4.40 mm, and 1.2 mm max height - optimized for high-density PCB layouts requiring low profile and thermal efficiency.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 15 | 1OE, 2OE | Active-low output-enable controls for Group 1 (pins 2–7, 9–10) and Group 2 (pins 11–14); tied to VCC via pull-up for power-up high-Z safety. |
| 2, 4, 6, 10, 12, 14 | 1A1–1A4, 2A1–2A2 | Noninverting input terminals - accept 5.5 V-tolerant signals regardless of VCC setting. |
| 3, 5, 7, 9, 11, 13 | 1Y1–1Y4, 2Y1–2Y2 | 3-state buffered outputs - drive loads up to ±8 mA at 3 V with balanced rise/fall times and <0.8 V ground bounce. |
| 8 | GND | Ground reference for all I/O and internal logic - must be low-impedance connection to minimize noise coupling. |
| 16 | VCC | Primary supply rail (2–5.5 V); requires local 0.1 µF bypass capacitor placed adjacent to pin for stable switching performance. |
Key Features
| Feature | Design Value |
|---|---|
| Mixed-voltage interface | 5.5 V-tolerant inputs enable direct connection to legacy 5 V controllers while operating at 3.3 V or 2.5 V VCC - eliminating external level shifters. |
| Controlled output drive | ±8 mA output strength at 3 V with slow-edge optimization reduces EMI and overshoot/undershoot - critical for LED matrix and segment drivers. |
| Power-down safety | Ioff circuitry disables all outputs when VCC = 0 V, limiting leakage to ≤5 µA per pin - prevents backfeeding and protects downstream circuitry during hot-swap or partial power loss. |
| Robust bus isolation | High-impedance state leakage ≤±5 µA and fast disable time (tdis ≤12.5 ns at 3.3 V) ensure clean bus arbitration in multi-driver systems like address/data expansion. |
| Latch-up immunity | Exceeds 250 mA per JESD17 - guarantees reliability under transient overvoltage or ground-bounce conditions in industrial environments. |
Applications
| LED Matrix Control | 7-Segment Display Control |
|---|---|
|
Use Scenario: Driving rows/columns of multiplexed LED arrays in signage or status panels with dynamic refresh rates ≥1 kHz. IC Role / Device Role: Hex buffer provides isolated, current-limited column drive while enabling/disabling groups via 1OE and 2OE for time-multiplexed scanning. Use Value: ±8 mA drive at 3.3 V eliminates need for external transistor arrays; 5.5 V-tolerant inputs accept PWM signals from 5 V microcontrollers without level shifting. |
Use Scenario: Controlling common-anode or common-cathode 7-segment displays in test equipment or industrial HMIs. IC Role / Device Role: Noninverting buffer translates MCU GPIO outputs to segment drive lines, with 3-state outputs enabling digit-by-digit multiplexing. Use Value: Sub-10 ns propagation delay ensures precise timing alignment across segments; low ground bounce (<0.8 V) prevents false digit activation during switching. |
| Memory Address Expansion | Low-Noise Bus Interface |
|
Use Scenario: Expanding address bus width from an MCU or FPGA to access larger external memory banks or peripheral registers. IC Role / Device Role: Hex buffer isolates and strengthens address signals before routing to multiple memory devices, with OE pins synchronized to chip-select timing. Use Value: Dual OE control allows independent gating of upper/lower address nibbles; 2 V–5.5 V operation matches diverse memory VCC requirements. |
Use Scenario: Interfacing between mixed-voltage subsystems (e.g., 5 V sensor hub and 3.3 V processor) while minimizing signal integrity degradation. IC Role / Device Role: Level-translating buffer with controlled slew rate and 5.5 V-tolerant inputs acts as a clean, low-noise bridge between voltage domains. Use Value: Balanced CMOS outputs reduce ringing on stubbed traces; ±2000 V HBM ESD rating ensures robustness in noisy industrial data acquisition paths. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar hex buffer/line driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC6T245RGYR | 6-bit dual-supply translator (A/B side VCC configurable); no 3-state grouping - all outputs share single OE. | Better for bidirectional level translation; less suitable for independent group enable in LED matrix row/column control. | Choose SN74LVC6T245RGYR only when bidirectional data flow and independent A/B voltage rails are required. |
| SN74AHC1G125DBVR | Single-channel 3-state buffer (SOT-23-5); requires six units for full hex function; 2–5.5 V VCC, 8 mA drive, but no dual-OE architecture. | Higher board area and BOM count; lacks integrated grouping - unsuitable for coordinated enable timing in display multiplexing. | Use SN74AHC1G125DBVR only for point-to-point buffering where space permits discrete placement and group control is unnecessary. |
Compared with SN74LV367ADGVR, SN74LVC6T245RGYR offers bidirectional translation but sacrifices independent group control, while SN74AHC1G125DBVR increases layout complexity and lacks native dual-OE synchronization - making SN74LV367ADGVR uniquely suited for coordinated bus expansion and multiplexed display driving.
Availability
SN74LV367ADGVR is available at Aetrix Electronics and suitable for LED matrix control, 7-segment display interfaces, memory address expansion, industrial bus interfacing, and low-noise signal buffering requiring stable component supply and long-term production continuity.
Supply support for SN74LV367ADGVR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of expertise in high-reliability industrial and automotive IC design.
The SN74LV367A product line was engineered for robust, low-power bus interfacing and display driving in mixed-voltage systems - emphasizing 3-state control precision, ESD resilience, and seamless voltage domain bridging.
FAQ
What is the maximum propagation delay of the SN74LV367ADGVR at 3.3 V operation?
The SN74LV367ADGVR has a maximum propagation delay (tpd) of 10 ns at VCC = 3.3 V with CL = 15 pF and TA = 25°C, as specified in Section 6.7 of the official datasheet. This value ensures reliable timing margins in 3.3 V bus expansion and display multiplexing applications where sub-12 ns latency is required.
Does the SN74LV367ADGVR support 5 V input signals while operating at 3.3 V VCC?
Yes, the SN74LV367ADGVR supports input voltages up to 5.5 V regardless of VCC setting - including when VCC = 3.3 V. This 5 V-tolerant input capability is explicitly documented in Section 6.3 (Recommended Operating Conditions) and enables direct interfacing with legacy 5 V microcontrollers without external level-shifting circuitry.
How does the dual output-enable architecture of the SN74LV367ADGVR improve display multiplexing?
The SN74LV367ADGVR's dual active-low OE inputs (1OE and 2OE) allow independent control of two functional groups: Group 1 (1A1–1Y3, 1A4, 1Y4) and Group 2 (2A1–2Y2). In LED matrix or 7-segment applications, this enables synchronized row/column blanking or digit-by-digit enable timing - reducing ghosting and improving contrast without additional logic gates.
What is the recommended bypass capacitor for the VCC pin of the SN74LV367ADGVR?
Texas Instruments recommends a 0.1 µF ceramic bypass capacitor placed as close as possible to the VCC pin (Pin 16) of the SN74LV367ADGVR, as stated in Section 9.3 of the datasheet. This minimizes power supply noise and stabilizes switching transients - especially critical given the device's 7 ns propagation delay and ±8 mA output drive capability.
Is the SN74LV367ADGVR pin-compatible with other packages in the SN74LV367A family?
No - the SN74LV367ADGVR uses the TVSOP-16 (DGV) package with 0.5 mm pitch and 3.60 mm × 4.40 mm body size, which is not mechanically or solder-reflow compatible with SOIC (D), SOP (NS), or TSSOP (PW) variants. While electrical functionality and pin functions are identical across packages, PCB layout and reflow profiles must be tailored to the DGV footprint.
SN74LV367ADGVR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LV
- Package/Case:
- 16-TFSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 2
- Number of Bits per Element:
- 2, 4 (Hex)
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 16mA, 16mA
- Voltage - Supply:
- 2V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TVSOP
SN74LV367ADGVR FAQ
1.How can I place an order for SN74LV367ADGVR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LV367ADGVR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of SN74LV367ADGVR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LV367ADGVR is usually 5 days.
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Once your SN74LV367ADGVR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LV367ADGVR?
For technical support, including SN74LV367ADGVR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LV367ADGVR requirements.
6.How does Aetrix verify that SN74LV367ADGVR is sourced from the original manufacturer or authorized distributors?
All SN74LV367ADGVR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LV367ADGVR meets industry standards.
7.What is the process for return or replacement of SN74LV367ADGVR?
All SN74LV367ADGVR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LV367ADGVR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LV367ADGVR part is unused and in its original packaging.
Return procedure for SN74LV367ADGVR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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