Texas Instruments SN74LVC112ANS
- Part No.:
- SN74LVC112ANS
- Manufacturer:
- Texas Instruments
- Category:
- Flip Flops
- Package:
- 16-SOIC (0.209", 5.30mm Width)
- Datasheet:
-
SN74LVC112ANS.pdf
- Description:
- IC FF JK TYPE DUAL 1BIT 16SO
- Quantity:
- Payment:

- Shipping:

Inventory:21,150
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Product details
Overview
SN74LVC112ANS from Texas Instruments is a dual negative-edge-triggered J-K flip-flop with independent clear and preset inputs, designed for 1.65V–3.6V operation. It delivers 4.8ns max propagation delay at 3.3V, supports 5.5V-tolerant inputs, and operates across –40°C to +125°C - enabling use in high-speed bus interface and I/O expansion circuits within notebooks and network switches.
For engineers reviewing the SN74LVC112ANS datasheet, SN74LVC112ANS pinout, SN74LVC112ANS application, or SN74LVC112ANS equivalent, key selection criteria include negative-edge clocking behavior, dual independent J-K sections with asynchronous control, 5.5V input tolerance for mixed-voltage translation, and SOP-16 package compatibility with legacy board layouts.
Technical Context
This device implements two independent, fully synchronous J-K flip-flops sharing no internal logic - each with dedicated CLK, J, K, PRE, CLR, Q, and Q̅ terminals. Clock triggering occurs on the negative edge only, and asynchronous PRE/CLR override all other inputs regardless of clock state.
It features Ioff protection (enabling back-drive safety when VCC = 0V), 5.5V-tolerant inputs compatible with 5V logic driving 3.3V systems, and guaranteed operation up to 150MHz at 3.3V with tpd ≤ 4.8ns - validated across –40°C to +125°C.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65V to 3.6V - enables direct integration into modern low-voltage digital subsystems without level-shifting. |
| Input Voltage Tolerance | Up to 5.5V - allows interfacing with legacy 5V logic families while powered from 3.3V rails. |
| Max Propagation Delay | 4.8ns at VCC = 3.3V, TA = 25°C - supports reliable 150MHz toggle operation in timing-critical paths. |
| Operating Temperature | –40°C to +125°C - qualified for industrial and extended-temperature embedded applications. |
| Output Drive Strength | ±24mA at VCC = 3.0V - sufficient to drive multiple LVC/LVT loads or small capacitive buses directly. |
| Ioff Protection | Active when VCC = 0V - prevents current backflow during partial power-down or hot-insertion scenarios. |
| ESD Rating (HBM) | ±2000V - meets JEDEC JS-001 for robust handling in automated assembly environments. |
Pinout & Package
SOP-16 (NS) package: 10.2mm × 7.8mm body size, 16-pin surface-mount with gull-wing leads; RoHS-compliant, NIPDAU finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1CLK, 2CLK | Clock Input | Negative-edge-triggered clock for respective flip-flop; accepts 0–5.5V swing regardless of VCC. |
| 1J / 1K / 2J / 2K | Data Inputs | Standard J/K control inputs; J=1,K=0 sets Q=1; J=0,K=1 resets Q=0; J=K=1 toggles Q on clock edge. |
| 1PRE / 2PRE | Asynchronous Preset | Active-low; forces corresponding Q high and Q̅ low immediately, overriding clock and data. |
| 1CLR / 2CLR | Asynchronous Clear | Active-low; forces corresponding Q low and Q̅ high immediately, overriding clock and data. |
| 1Q / 1Q̅ / 2Q / 2Q̅ | Complementary Outputs | True and inverted outputs per section; rail-to-rail CMOS swing referenced to VCC/GND. |
| VCC | Power Supply | Single supply pin for both flip-flops; bypassing with 0.1μF capacitor required near pin. |
| GND | Ground Reference | Common return path for all signals and power; must be low-impedance for noise immunity. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 1.65V–3.6V operation enables drop-in replacement in 1.8V, 2.5V, and 3.3V systems without redesign. |
| 5.5V-tolerant inputs | Eliminates external level shifters when interfacing 5V microcontrollers or FPGAs to 3.3V logic domains. |
| Negative-edge triggering | Enables precise synchronization to falling edges of clocks or control signals in pipeline architectures. |
| Ioff protection | Prevents damaging current flow between powered and unpowered sections in multi-rail systems. |
| High-speed toggle capability | Guaranteed 150MHz toggle frequency at 3.3V supports real-time state machine and counter designs. |
Applications
| Server Memory Buffering | Notebook I/O Expansion |
|---|---|
Use Scenario: Latching address/control signals between CPU and DDR memory controller in compact server modules. IC Role / Device Role / Timing Role: Dual J-K flip-flop provides synchronized, glitch-free storage of critical bus enable and bank-select lines. Use Value: 4.8ns tpd ensures setup/hold compliance at 150MHz clock rates; 5.5V input tolerance accommodates legacy BIOS SPI flash interfaces. |
Use Scenario: Expanding GPIO count for touchpad, keyboard, and sensor hub control in space-constrained notebook PCBs. IC Role / Device Role / Timing Role: Configured as toggle or D-type latches to extend microcontroller I/O without firmware overhead. Use Value: SOP-16 footprint matches legacy layout constraints; –40°C to +125°C rating covers full thermal envelope of mobile platforms. |
| Industrial Network Switch Control | Electronic Point-of-Sale (POS) Interface |
Use Scenario: Managing port enable/disable sequencing and link status handshaking in managed Ethernet switch ASIC support circuitry. IC Role / Device Role / Timing Role: Asynchronous PRE/CLR pins implement hardware reset coordination across multiple PHY lanes. Use Value: Independent clear/preset per section allows staggered initialization; Ioff protection secures isolation during hot-swap events. |
Use Scenario: Interfacing barcode scanner, receipt printer, and cash drawer drivers to low-pin-count MCU in compact POS terminals. IC Role / Device Role / Timing Role: J-K configuration used for debounced switch detection and bidirectional data strobing. Use Value: ±24mA drive strength directly drives LED indicators and solenoid drivers; 1.65V min VCC supports battery-backed operation. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual J-K flip-flop applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC112ADR | SOIC-16 (D) package; identical electrical specs and pinout; 2500-piece tape-and-reel vs. NS package's 2000-piece reel. | Same functional role but requires PCB footprint change; preferred for high-volume automated assembly with standard SOIC tooling. | Select SN74LVC112ADR if SOIC-16 is already standardized in your production line and thermal dissipation >117.5°C/W is acceptable. |
| SN74LVC112APWR | TSSOP-16 (PW) package; same specs; 2000-piece tape-and-reel; slightly smaller body (5.0mm × 6.4mm) than NS (10.2mm × 7.8mm). | Enables higher board density; requires requalification of solder profile due to finer pitch (0.65mm vs. 1.27mm). | Choose SN74LVC112APWR when PCB area is constrained and you can validate reflow for 0.65mm-pitch TSSOP. |
Compared with SN74LVC112ANS, SN74LVC112ADR offers identical performance in a more widely supported SOIC package but increases thermal resistance by ~0.6°C/W; SN74LVC112APWR reduces footprint by 61% but demands tighter process control for assembly yield.
Availability
SN74LVC112ANS is available at Aetrix Electronics and suitable for server memory buffering, notebook I/O expansion, and industrial network switch control requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SN74LVC112ANS includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions with over 50 years of innovation in high-reliability digital ICs.
The SN74LVC112A belongs to TI's LVC (Low-Voltage CMOS) logic family, engineered for interoperability across 1.65V–3.6V systems and mixed-voltage signal translation in computing and communications infrastructure.
FAQ
What is the maximum clock frequency supported by SN74LVC112ANS?
The SN74LVC112ANS supports a maximum clock frequency of 150MHz at VCC = 3.3V and TA = 25°C, with guaranteed operation down to 120MHz across the full –40°C to +125°C temperature range. This is validated by tpd ≤ 4.8ns and tw ≥ 3.3ns pulse width requirements in the official TI datasheet SCAS289O.
Does SN74LVC112ANS support 5V input signals while operating at 3.3V VCC?
Yes, SN74LVC112ANS supports input voltages up to 5.5V regardless of VCC level - a documented feature enabling direct interfacing with 5V logic families such as TTL or older microcontrollers without external level shifters. This is specified under "Inputs accept voltages to 5.5V" in the Features section of the TI datasheet.
What is the function of the Ioff feature in SN74LVC112ANS?
The Ioff feature in SN74LVC112ANS disables output buffers and isolates inputs when VCC = 0V, preventing current backflow from live system buses into an unpowered device. This protects downstream circuitry during partial power-down or hot-swap conditions and is explicitly confirmed in Section 7.3 of the TI datasheet.
Can SN74LVC112ANS be used as a toggle flip-flop?
Yes, SN74LVC112ANS can operate as a toggle flip-flop by connecting both J and K inputs high on either section. The device's functional table (Table 7-1) confirms that J=K=1 causes Q to toggle on each negative clock edge - a behavior verified across all operating conditions including –40°C to +125°C.
What package type does SN74LVC112ANS use, and is it RoHS-compliant?
SN74LVC112ANS uses the SOP-16 (NS) package with 10.2mm × 7.8mm body size and gull-wing leads. It is RoHS-compliant with NIPDAU lead finish and MSL Level-1 rating, as confirmed in TI's Package Option Addendum dated May 2026 - matching the orderable part number SN74LVC112ANSR.B.
SN74LVC112ANS Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVC
- Package/Case:
- 16-SOIC (0.209", 5.30mm Width)
- Packaging:
- Bulk
- Product Status:
- Active
- Function:
- Set(Preset) and Reset
- Type:
- JK Type
- Output Type:
- Complementary
- Number of Elements:
- 2
- Number of Bits per Element:
- 1
- Clock Frequency:
- 150 MHz
- Max Propagation Delay @ V, Max CL:
- 5.9ns @ 3.3V, 50pF
- Trigger Type:
- Negative Edge
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 1.65V ~ 3.6V
- Current - Quiescent (Iq):
- 10 µA
- Input Capacitance:
- 4.5 pF
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-SO
SN74LVC112ANS FAQ
1.How can I place an order for SN74LVC112ANS through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LVC112ANS on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LVC112ANS reliable?
The price and inventory of SN74LVC112ANS are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LVC112ANS is usually 5 days.
3.What payment methods are accepted for SN74LVC112ANS?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LVC112ANS transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LVC112ANS?
SN74LVC112ANS orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LVC112ANS order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LVC112ANS?
For technical support, including SN74LVC112ANS datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LVC112ANS requirements.
6.How does Aetrix verify that SN74LVC112ANS is sourced from the original manufacturer or authorized distributors?
All SN74LVC112ANS products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LVC112ANS meets industry standards.
7.What is the process for return or replacement of SN74LVC112ANS?
All SN74LVC112ANS units undergo pre-shipment inspection (PSI). If there is an issue with SN74LVC112ANS, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LVC112ANS part is unused and in its original packaging.
Return procedure for SN74LVC112ANS:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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