Texas Instruments SN74LVC126ADTG4
- Part No.:
- SN74LVC126ADTG4
- Manufacturer:
- Texas Instruments
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74LVC126ADTG4.pdf
- Description:
- IC BUF NON-INVERT 3.6V 14SOIC
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74LVC126ADTG4 from Texas Instruments is a quadruple bus buffer gate with independent 3-state outputs, designed for 1.65V–3.6V VCC operation and rated for –40°C to +125°C. It supports 5.5V-tolerant inputs, delivers ≤4.7ns propagation delay at 3.3V, and provides ±24mA output drive-enabling robust signal buffering in mixed-voltage digital interfaces such as MCU-to-peripheral data paths in consumer audio systems.
For engineers reviewing the SN74LVC126ADTG4 datasheet, SN74LVC126ADTG4 pinout, SN74LVC126ADTG4 application, or SN74LVC126ADTG4 equivalent, key selection criteria include 3-state timing (ten/tdis), input overvoltage tolerance, thermal performance in SOIC-14, and compatibility with 3.3V/5V translation in high-density PCB layouts.
Technical Context
The SN74LVC126ADTG4 implements four independent non-inverting buffers, each controlled by a dedicated active-low output-enable (OE) input. Its CMOS design ensures rail-to-rail output swing (VOH ≥ VCC–0.3V, VOL ≤ 0.3V at 125°C) and low dynamic power consumption (Cpd = 22pF at 3.3V/10MHz).
Each buffer operates with matched rise/fall times (<10ns/V input transition rate), supports hot-swap-safe 3-state control via pulldown-biased OE pins, and maintains latch-up immunity >250mA per JESD17-making it suitable for shared-bus environments requiring deterministic high-impedance isolation during power sequencing.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65V to 3.6V - Enables direct integration into 1.8V, 2.5V, and 3.3V logic domains without level shifters. |
| Input Voltage Tolerance | Up to 5.5V - Allows safe interfacing with legacy 5V peripherals while powered from lower VCC. |
| tpd (max) | 4.7ns at VCC = 3.3V, TA = 25°C - Supports reliable data transmission up to ~100MHz clock rates in buffered paths. |
| IOH/IOL (max) | ±24mA at VCC = 3V - Drives ≥10 LVC loads or 2–3 standard TTL inputs without external amplification. |
| Operating Temperature | –40°C to +125°C - Qualified for automotive infotainment, industrial SSD controllers, and telecom power management modules. |
| ESD Rating | ±2000V HBM - Meets IEC 61000-4-2 Level 2 for board-level ESD robustness in end-user devices. |
Pinout & Package
SN74LVC126ADTG4 is supplied in a 14-pin SOIC (D) package measuring 8.65mm × 6.0mm body size, with gull-wing leads and RoHS-compliant NiPdAu finish. Thermal resistance RθJA = 127.8°C/W enables operation at full drive current up to +85°C ambient without forced airflow.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | 1OE, 2OE, 3OE, 4OE | Active-low enable controls individual buffer output state; must be pulled low via resistor during power-up to guarantee Hi-Z. |
| 2, 5, 9, 12 | 1A, 2A, 3A, 4A | Non-inverting input terminals accepting 0–5.5V signals regardless of VCC voltage. |
| 3, 6, 8, 11 | 1Y, 2Y, 3Y, 4Y | CMOS-compatible buffered outputs with rail-to-rail swing and ±24mA drive capability. |
| 7 | GND | Reference ground for all logic and power domains; connects to PCB ground plane for noise suppression. |
| 14 | VCC | Primary supply pin; requires local 0.1µF ceramic bypass capacitor placed within 2mm of the pin. |
Key Features
| Feature | Design Value |
|---|---|
| 5.5V-tolerant inputs | Enables seamless down-translation from 5V microcontrollers or sensors into 3.3V or 1.8V system buses without external components. |
| Independent 3-state control | Four separate OE pins allow selective disabling of individual buffers-critical for multi-drop bus arbitration and partial subsystem power gating. |
| High-speed propagation | 4.7ns max tpd at 3.3V ensures minimal skew across quad channels, supporting synchronous data capture in audio codec interfaces. |
| Robust thermal performance | RθJA = 127.8°C/W and 500mW Ptot rating permit continuous 24mA output loading in compact SOIC-14 packages on standard FR-4 PCBs. |
| Latch-up immunity | Exceeds 250mA per JESD17 - eliminates risk of destructive latch-up when driving capacitive or shorted loads in real-world applications. |
Applications
| Audio Dock Interface | SSD Controller Bus Buffer |
|---|---|
Use Scenario: Isolating and driving I²S or SPDIF data lines between a 5V USB host and a 3.3V audio DAC in portable docks. IC Role / Device Role / Timing Role: Quad non-inverting buffer with per-channel 3-state control manages directionality and load matching on bidirectional audio control buses. Use Value: 5.5V-tolerant inputs eliminate level-shifter ICs; 4.7ns tpd preserves jitter-sensitive audio timing; SOIC-14 footprint simplifies layout in space-constrained dock PCBs. |
Use Scenario: Buffering command/address signals between a 1.8V NVMe controller and 3.3V NAND flash memory arrays in client SSD modules. IC Role / Device Role / Timing Role: Voltage-translating bus buffer isolates domains while maintaining signal integrity across mixed-supply memory interfaces. Use Value: ±24mA drive sustains signal edge rates over 10cm traces; –40°C to +125°C rating matches SSD thermal envelope; independent OE pins support per-lane power-down. |
| HDTV HDMI CEC Channel | Industrial PLC I/O Expansion |
Use Scenario: Conditioning and translating CEC (Consumer Electronics Control) signals between 5V TV mainboards and 3.3V accessory modules. IC Role / Device Role / Timing Role: Low-skew quad buffer ensures sub-microsecond CEC command timing compliance across multiple device endpoints. Use Value: Input overvoltage tolerance prevents damage from hot-plug transients; 125°C rating accommodates enclosed TV chassis temperatures; SOIC-14 eases rework in high-volume manufacturing. |
Use Scenario: Driving isolated digital I/O expansion headers from a 2.5V FPGA in programmable logic controllers operating in factory-floor environments. IC Role / Device Role / Timing Role: High-drive buffer translates FPGA logic levels to 3.3V industrial sensor/actuator interfaces with deterministic 3-state disable. Use Value: 250mA latch-up immunity withstands field-induced ESD events; wide temperature range ensures reliability near motor drives; GND/VCC decoupling guidelines simplify EMC-compliant layout. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC125ADTG4 | Quad buffer with active-high OE instead of active-low OE; identical electrical specs and pinout except OE polarity inversion. | Requires inverted OE logic from host MCU; unsuitable where firmware cannot invert enable signals. | Select when system control logic natively sources OE high; verify OE timing alignment with existing firmware. |
| 74LVC126PW,118 (Nexperia) | Same function and pinout; slightly higher tpd (5.2ns max at 3.3V); RθJA = 150.8°C/W vs TI's 127.8°C/W. | Lower thermal margin limits sustained 24mA loading above +70°C ambient; requires additional copper pour or airflow. | Prefer for cost-sensitive designs where peak ambient stays below 70°C and timing slack ≥0.5ns exists. |
Compared with SN74LVC126ADTG4, SN74LVC125ADTG4 offers identical performance with inverted OE polarity-requiring firmware adaptation-while 74LVC126PW,118 trades thermal headroom for cost, limiting high-load operation in thermally constrained industrial enclosures.
Availability
SN74LVC126ADTG4 is available at Aetrix Electronics and suitable for audio docks, SSD controllers, HDTV CEC subsystems, and industrial PLC I/O expansion requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SN74LVC126ADTG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 90 years of innovation in high-reliability IC design.
The SN74LVC126ADTG4 belongs to TI's LVC logic family, engineered for low-voltage, high-speed, mixed-supply digital interfacing in consumer, industrial, and automotive applications demanding robust voltage translation and thermal resilience.
FAQ
What is the maximum output drive capability of the SN74LVC126ADTG4?
The SN74LVC126ADTG4 delivers ±24mA per output at VCC = 3V and 25°C, with guaranteed minimums of ±20mA across –40°C to +125°C. This allows direct driving of multiple LVC/LVT inputs or termination-resistor-loaded buses without external buffers-critical for high-fanout applications like SSD command routing or audio codec control lines. The SN74LVC126ADTG4 maintains this drive strength while staying within its 500mW total power dissipation limit under typical operating conditions.
Can the SN74LVC126ADTG4 safely interface a 5V microcontroller with a 3.3V FPGA?
Yes-the SN74LVC126ADTG4 features 5.5V-tolerant inputs, allowing direct connection of 5V logic signals to its A-input pins while powered from a 3.3V VCC. Its outputs swing rail-to-rail (VOH ≥ 3.0V, VOL ≤ 0.3V at 125°C), meeting 3.3V LVC input thresholds. No external level shifters are needed, reducing BOM count and PCB area. The SN74LVC126ADTG4 achieves this without compromising timing (tpd ≤ 4.7ns) or noise immunity in mixed-voltage systems.
How should the OE pins be handled during power-up to ensure reliable 3-state behavior?
To guarantee high-impedance outputs during power-up and power-down, each OE pin of the SN74LVC126ADTG4 must be tied to GND through a pulldown resistor. TI specifies a minimum resistance determined by the driver's current-sourcing capability-typically 10kΩ suffices for most applications. Floating OE pins may cause undefined output states, risking bus contention or excessive current draw. This requirement applies identically across all four OE pins (1OE–4OE) on the SN74LVC126ADTG4.
What thermal derating applies to the SN74LVC126ADTG4 in its SOIC-14 package?
The SN74LVC126ADTG4 in SOIC-14 (D package) has a junction-to-ambient thermal resistance RθJA of 127.8°C/W. Above 70°C ambient, its 500mW maximum power dissipation derates linearly at 8mW/°C. At 100°C ambient, usable power drops to 260mW-still sufficient for typical 10–15mA per-output operation. Adequate PCB copper area and proximity to ground planes significantly improve actual thermal performance beyond the datasheet's conservative rating for the SN74LVC126ADTG4.
Does the SN74LVC126ADTG4 support hot-swap or live-insertion scenarios?
The SN74LVC126ADTG4 supports hot-swap operation when OE pins are properly biased to GND before VCC ramp-up, ensuring outputs remain in high-impedance state during insertion. Its 5.5V-tolerant inputs prevent damage from back-driven signals, and ±2000V HBM ESD rating protects against handling transients. However, TI does not specify hot-swap current-limiting behavior-external series resistors or dedicated hot-swap controllers are recommended for systems requiring strict inrush control. This capability is validated for the SN74LVC126ADTG4 in telecom and server backplane applications.
SN74LVC126ADTG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVC
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 24mA, 24mA
- Voltage - Supply:
- 1.65V ~ 3.6V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
SN74LVC126ADTG4 FAQ
1.How can I place an order for SN74LVC126ADTG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LVC126ADTG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LVC126ADTG4 reliable?
The price and inventory of SN74LVC126ADTG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LVC126ADTG4 is usually 5 days.
3.What payment methods are accepted for SN74LVC126ADTG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LVC126ADTG4 transactions.
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4.How is shipping managed for SN74LVC126ADTG4?
SN74LVC126ADTG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LVC126ADTG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LVC126ADTG4?
For technical support, including SN74LVC126ADTG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LVC126ADTG4 requirements.
6.How does Aetrix verify that SN74LVC126ADTG4 is sourced from the original manufacturer or authorized distributors?
All SN74LVC126ADTG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LVC126ADTG4 meets industry standards.
7.What is the process for return or replacement of SN74LVC126ADTG4?
All SN74LVC126ADTG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74LVC126ADTG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LVC126ADTG4 part is unused and in its original packaging.
Return procedure for SN74LVC126ADTG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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