Texas Instruments SN74LVC138AGQNR
- Part No.:
- SN74LVC138AGQNR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 20-VFBGA
- Datasheet:
-
SN74LVC138AGQNR.pdf
- Description:
- IC DECODER/DEMUX 1X3:8 20BGA
- Quantity:
- Payment:

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Product details
Overview
SN74LVC138AGQNR from Texas Instruments is a 3-line to 8-line decoder/demultiplexer IC operating from 1.65 V to 3.6 V, with 5.8 ns max propagation delay at 3.3 V, inputs tolerant to 5.5 V, and active-low G2A/G2B plus active-high G1 enables. It drives LED matrix column selection in embedded display systems.
For engineers reviewing the SN74LVC138AGQNR datasheet, SN74LVC138AGQNR pinout, SN74LVC138AGQNR application, or SN74LVC138AGQNR equivalent, key selection criteria include supply voltage range, enable logic configuration (2× active-low + 1× active-high), output drive capability (±24 mA), propagation delay vs. VCC, and compatibility with mixed-voltage 3.3 V/5 V interface environments.
Technical Context
The SN74LVC138AGQNR implements binary decoding of three select inputs (A, B, C) to assert exactly one of eight active-low outputs (Y0–Y7), with all outputs high when any enable is inactive. Its enable architecture-G1 (active-high), G2A and G2B (both active-low)-enables hierarchical expansion without external inverters, supporting 24-line decoding natively and 32-line with one inverter.
It uses advanced CMOS logic with balanced output drive, latch-up immunity exceeding 250 mA per JESD17, and input tolerance up to 5.5 V independent of VCC. Output ground bounce (VOLP < 0.8 V) and undershoot (VOHV > 2 V) are characterized at 3.3 V, ensuring signal integrity in fast-switching applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 1.65 V to 3.6 V - Enables direct integration into low-voltage I/O domains (e.g., 1.8 V FPGA banks) while maintaining full functionality. |
| Max Propagation Delay | 5.8 ns at VCC = 3.3 V - Supports high-speed memory decoding and real-time LED scanning with sub-10 ns timing margins. |
| Input Voltage Tolerance | Up to 5.5 V - Allows direct interfacing with legacy 5 V logic or microcontrollers without level shifters. |
| Output Drive Current | ±24 mA at VCC = 3.0 V - Sufficient for direct low-side driving of LED columns or TTL-compatible loads. |
| Enable Logic | G1 (active-high), G2A & G2B (active-low) - Provides flexible hierarchical enable control for multi-device decoding trees. |
| Operating Temperature | –40°C to +85°C - Qualified for industrial-grade embedded systems including factory automation and building controls. |
| ESD Rating | 2000 V HBM, 1000 V CDM - Meets standard handling requirements for automated assembly and field-replaceable modules. |
Pinout & Package
SN74LVC138AGQNR is packaged in a 16-pin TVSOP (DGV) with nominal body size 3.60 mm × 4.40 mm and 0.65 mm lead pitch. Pin numbering follows standard DGV top-view orientation.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 | G2B | Active-low enable input; must be LOW for device operation - used for hierarchical disable or data gating in demux mode. |
| 2 | G2A | Active-low enable input; complements G2B for dual-enable control - supports OR-ed enable trees across multiple decoders. |
| 3 | G1 | Active-high enable input; must be HIGH for device operation - primary global enable for system-level power gating. |
| 4 | C | Most significant select input (MSB) - defines bit position for 3-bit binary address decoding (CBA = Y0–Y7). |
| 5 | B | Mid-significance select input - contributes to 3-bit address resolution; tied with A/C to configure output mapping. |
| 6 | A | Least significant select input (LSB) - completes 3-bit address; determines which of eight outputs is asserted low. |
| 7 | Y7 | Active-low decoded output (MSB) - sinks current when selected; used for highest-addressed channel in memory or I/O expansion. |
| 8 | GND | Ground reference - must be connected to system common; decoupling capacitor required within 5 mm of pin. |
| 9 | Y6 | Active-low decoded output - provides dedicated low-side drive path for peripheral selection or LED column control. |
| 10 | Y5 | Active-low decoded output - electrically identical to Y0–Y7; no internal differentiation - all outputs share same drive strength. |
| 11 | Y4 | Active-low decoded output - asserted only when CBA = 100₂; used in fixed-function address decoding schemes. |
| 12 | Y3 | Active-low decoded output - supports 1-of-8 routing in bus multiplexing or sensor array addressing. |
| 13 | Y2 | Active-low decoded output - low-impedance sink path (24 mA capable) for driving discrete loads directly. |
| 14 | Y1 | Active-low decoded output - shares identical timing and electrical specs with Y0–Y7; no skew beyond 1 ns. |
| 15 | Y0 | Active-low decoded output (LSB) - asserted when CBA = 000₂; commonly used as default or reset-select line. |
| 16 | VCC | Positive supply rail - requires local 0.1 µF ceramic bypass capacitor; noise sensitivity increases above 3.6 V. |
Key Features
| Feature | Design Value |
|---|---|
| 3-to-8 decoding with 3 enable inputs | Enables scalable address decoding: 24-line without inverters, 32-line with one inverter - reduces BOM count and board area. |
| 1.65 V to 3.6 V supply range | Supports direct connection to modern low-voltage processors (e.g., ARM Cortex-M, RISC-V SoCs) without voltage translation. |
| 5.5 V-tolerant inputs | Eliminates need for external level shifters when interfacing with 5 V sensors, legacy microcontrollers, or industrial I/O. |
| 5.8 ns max tpd at 3.3 V | Meets tight timing budgets in high-speed memory subsystems and real-time LED refresh circuits (≥1 kHz frame rates). |
| Latch-up immunity >250 mA | Ensures robustness against transient overcurrent events in noisy industrial environments or hot-plug scenarios. |
| Low ground bounce (VOLP < 0.8 V) | Maintains signal integrity during simultaneous switching; critical for stable operation in dense PCB layouts with shared ground planes. |
Applications
| LED Matrix Column Driver | Memory Address Decoder |
|---|---|
|
Use Scenario: Driving 8-column LED dot-matrix displays in industrial HMIs and consumer panels. IC Role / Device Role / Timing Role: Low-side column selector that asserts exactly one Yx output low per scan cycle, enabling sequential column illumination. Use Value: Eliminates need for external transistor arrays; ±24 mA drive supports common-cathode LEDs directly at 3.3 V. |
Use Scenario: Translating 3-bit address lines into chip-select signals for 8 SRAM or flash devices in embedded controllers. IC Role / Device Role / Timing Role: High-speed address decoder minimizing added latency between CPU address assertion and memory enable. Use Value: 5.8 ns propagation delay ensures effective system delay remains negligible versus typical 15–25 ns memory access times. |
| Industrial I/O Expansion | Factory Automation Bus Multiplexer |
|
Use Scenario: Selecting among 8 analog sensor inputs or digital actuator channels in PLC modules. IC Role / Device Role / Timing Role: Digital selector enabling one of eight parallel paths based on controller GPIO outputs. Use Value: 5.5 V input tolerance allows direct connection to 5 V sensor buses; 3.6 V max VCC aligns with isolated 3.3 V logic rails. |
Use Scenario: Routing CAN, RS-485, or SPI signals to one of eight field devices in modular automation racks. IC Role / Device Role / Timing Role: Demultiplexer using G1 as data input and A/B/C as channel address - converts serial stream to parallel selection. Use Value: Active-low enables (G2A/G2B) allow daisy-chained enable control across rack-mounted modules without additional logic. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder/demultiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC138N | Wider VCC range (2 V–6 V), slower speed (24 ns @ 4.5 V), no 5.5 V input tolerance. | Suitable for legacy 5 V-only systems; not recommended for mixed-voltage or sub-2 V logic domains. | Choose SN74HC138N only if operating strictly at 5 V and timing budget exceeds 20 ns. |
| 74LVC138PW | Identical electrical specs and pinout; packaged in TSSOP-16 (5.00 mm × 4.40 mm) instead of TVSOP-16. | Same functional behavior but larger footprint; preferred where reflow profile or mechanical clearance favors TSSOP. | Select 74LVC138PW when board layout constraints prohibit TVSOP's 3.6 mm width or require higher thermal mass. |
Compared with SN74HC138N, SN74LVC138AGQNR delivers 4× faster propagation and 5.5 V input tolerance for mixed-voltage designs; compared with 74LVC138PW, it offers identical performance in a 22% smaller TVSOP package ideal for space-constrained industrial modules.
Availability
SN74LVC138AGQNR is available at Aetrix Electronics and suitable for LED matrix drivers, memory address decoders, and industrial I/O expansion requiring stable component supply, long-term lifecycle support, and RoHS-compliant packaging.
Supply support for SN74LVC138AGQNR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions for industrial, automotive, and communications markets.
The SN74LVC138AGQNR belongs to TI's LVC logic family, engineered for low-voltage, high-speed, mixed-signal interface applications where power efficiency, timing precision, and voltage translation are critical.
FAQ
What is the maximum supply voltage for SN74LVC138AGQNR?
The absolute maximum supply voltage for SN74LVC138AGQNR is 6.5 V, but the recommended operating range is 1.65 V to 3.6 V. Operation above 3.6 V risks parametric degradation and reduced reliability. All timing and drive specifications in the datasheet are guaranteed only within the 1.65–3.6 V range. Exceeding 3.6 V voids warranty and may cause permanent damage.
Can SN74LVC138AGQNR interface directly with 5 V microcontrollers?
Yes, SN74LVC138AGQNR accepts input voltages up to 5.5 V regardless of VCC level, making it compatible with 5 V GPIOs without level shifters. Inputs A, B, C, G1, G2A, and G2B all tolerate 5.5 V. However, outputs remain referenced to VCC (max 3.6 V), so downstream 5 V logic must accept 3.3 V–compatible high levels.
How does the enable logic work on SN74LVC138AGQNR?
SN74LVC138AGQNR requires G1 = HIGH, G2A = LOW, and G2B = LOW simultaneously to activate decoding. If any enable is violated, all outputs (Y0–Y7) go HIGH. This 2-active-low + 1-active-high scheme simplifies cascading: G1 of a lower-level decoder can be driven by Yx of a higher-level one, enabling 24-line decoding without external inverters.
What is the output drive capability of SN74LVC138AGQNR?
SN74LVC138AGQNR provides ±24 mA output drive at VCC = 3.0 V, with VOL ≤ 0.55 V and VOH ≥ 2.2 V under those conditions. This allows direct driving of LEDs, small relays, or TTL inputs. Outputs are push-pull CMOS, not open-drain, so they actively drive both HIGH and LOW states without external pull-ups.
Is SN74LVC138AGQNR suitable for LED matrix applications?
Yes, SN74LVC138AGQNR is explicitly validated for LED matrix column selection. Its active-low outputs sink current to illuminate common-cathode LEDs, and its 5.8 ns propagation delay supports high-refresh-rate scanning. The datasheet cites "LED Displays" as a primary application, and Figure 3 shows a working LED matrix driver implementation using SN74LVC138A.
SN74LVC138AGQNR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVC
- Package/Case:
- 20-VFBGA
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 24mA, 24mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 1.65V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 20-BGA MICROSTAR JUNIOR (4x3)
SN74LVC138AGQNR FAQ
1.How can I place an order for SN74LVC138AGQNR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LVC138AGQNR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LVC138AGQNR reliable?
The price and inventory of SN74LVC138AGQNR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LVC138AGQNR is usually 5 days.
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5.How can I obtain technical support or documentation for SN74LVC138AGQNR?
For technical support, including SN74LVC138AGQNR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LVC138AGQNR requirements.
6.How does Aetrix verify that SN74LVC138AGQNR is sourced from the original manufacturer or authorized distributors?
All SN74LVC138AGQNR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LVC138AGQNR meets industry standards.
7.What is the process for return or replacement of SN74LVC138AGQNR?
All SN74LVC138AGQNR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LVC138AGQNR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LVC138AGQNR part is unused and in its original packaging.
Return procedure for SN74LVC138AGQNR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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