Texas Instruments SN74LVC138APWRG4
- Part No.:
- SN74LVC138APWRG4
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74LVC138APWRG4.pdf
- Description:
- IC DECODER/DEMUX 1X3:8 16TSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74LVC138APWRG4 from Texas Instruments is a 3-line to 8-line decoder/demultiplexer IC operating from 1.65 V to 3.6 V, with 5.8 ns max propagation delay at 3.3 V, inputs tolerant to 5.5 V, and active-low dual-enable plus active-high enable architecture. It drives LED matrix column selection in low-side configurations with precise single-output activation.
For engineers reviewing the SN74LVC138APWRG4 datasheet, SN74LVC138APWRG4 pinout, SN74LVC138APWRG4 application, or SN74LVC138APWRG4 equivalent, key selection criteria include supply voltage range (1.65–3.6 V), input overvoltage tolerance (5.5 V), propagation delay (≤6.7 ns at 3.3 V), output drive capability (±24 mA), and TSSOP-16 package compatibility with high-density PCB layouts.
Technical Context
The SN74LVC138APWRG4 implements a binary-decoded 3-to-8 logic function where inputs A (LSB), B, and C (MSB) select one of eight active-low outputs (Y0–Y7). All outputs remain HIGH unless all three enables-G1 (active-high), G2A and G2B (both active-low)-are simultaneously asserted.
Its CMOS design supports mixed-voltage interfacing: 3.3-V or 5-V controllers can drive inputs while the device operates at 1.65–3.6 V. Enable inputs double as demultiplexing data paths, enabling cascaded decoding (e.g., 24-line without external inverters) and flexible signal routing in memory and I/O expansion systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage | 1.65 V to 3.6 V - Enables direct integration into 1.8-V and 3.3-V logic domains without level shifters. |
| Input Voltage Range | 0 V to 5.5 V - Allows safe interfacing with legacy 5-V microcontrollers or FPGAs without external clamping. |
| Max Propagation Delay | 5.8 ns at VCC = 3.3 V - Supports >100 MHz address decoding in high-speed memory subsystems. |
| Output Drive | ±24 mA at VCC = 3.0 V - Sufficient for direct LED column sinking (e.g., 20-mA segments) without external buffers. |
| Logic Family | LVC (Low-Voltage CMOS) - Ensures rail-to-rail output swing, low static current (<10 µA), and ESD robustness (2000-V HBM). |
| Operating Temperature | –40°C to +85°C - Qualified for industrial-grade embedded control, automation, and power infrastructure applications. |
Pinout & Package
TSSOP-16 package (4.4 mm × 5.0 mm body, 0.65 mm pitch), lead-free (NiPdAu), moisture sensitivity level 1, RoHS compliant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (G2A) | Active-low enable A | Must be LOW to activate decoder; used with G2B and G1 for hierarchical enable control. |
| 2 (G2B) | Active-low enable B | Second active-low enable; both G2A and G2B must be LOW for output enable. |
| 3 (G1) | Active-high enable | Must be HIGH to activate decoder; complements dual active-low enables for flexible gating. |
| 4 (C) | Select input C (MSB) | Most significant bit of 3-bit address bus; determines upper/lower half of Y0–Y7 output group. |
| 5 (B) | Select input B | Mid-bit of address bus; combined with A and C to uniquely select one of eight outputs. |
| 6 (A) | Select input A (LSB) | Least significant bit; final bit resolving exact output line (e.g., A=0,B=1,C=0 → Y2). |
| 7 (Y7) | Active-low output 7 | Only output driven LOW when A=B=C=1; others remain HIGH (open-drain behavior not present). |
| 8 (GND) | Ground reference | Primary return path for all internal logic and output currents; requires low-impedance PCB plane. |
| 9 (Y6) | Active-low output 6 | Asserted LOW for address 110₂; shares same timing and drive specs as all Yx outputs. |
| 10 (Y5) | Active-low output 5 | Asserted LOW for address 101₂; identical electrical characteristics across all eight outputs. |
| 11 (Y4) | Active-low output 4 | Asserted LOW for address 100₂; no output skew >1 ns between Y0–Y7 at 3.3 V. |
| 12 (Y3) | Active-low output 3 | Asserted LOW for address 011₂; supports simultaneous multi-output disable via enable pins. |
| 13 (Y2) | Active-low output 2 | Asserted LOW for address 010₂; compatible with standard CMOS load conditions (30 pF, 500 Ω). |
| 14 (Y1) | Active-low output 1 | Asserted LOW for address 001₂; VOL ≤ 0.4 V at 8 mA ensures solid logic LOW under full load. |
| 15 (Y0) | Active-low output 0 (LSB) | Asserted LOW for address 000₂; VOH ≥ VCC – 0.2 V guarantees noise margin >0.4 V at 3.3 V. |
| 16 (VCC) | Supply voltage | Power rail for core logic and output drivers; requires local 0.1-µF ceramic bypass capacitor. |
Key Features
| Feature | Design Value |
|---|---|
| Wide VCC range | 1.65 V to 3.6 V operation enables drop-in use in both 1.8-V and 3.3-V systems without redesign. |
| 5.5-V-tolerant inputs | Eliminates need for external level translators when interfacing with 5-V legacy controllers or sensors. |
| Sub-6-ns propagation | 5.8 ns max tpd at 3.3 V ensures negligible system delay in high-speed memory decode paths. |
| Three independent enables | G1 (HI), G2A/G2B (LO) allow hierarchical decoding (e.g., 24-line with no external inverters). |
| High noise immunity | VOLP < 0.8 V and VOHV > 2 V at 3.3 V suppress ground bounce and undershoot in noisy environments. |
Applications
| LED Matrix Column Driver | Memory Address Decoder |
|---|---|
|
Use Scenario: Driving 8-column common-anode LED matrix in industrial HMI panels with microcontroller GPIO. IC Role / Device Role / Timing Role: Low-side column selector; asserts exactly one Yx output LOW per 3-bit address cycle to illuminate single column. Use Value: Prevents ghosting by ensuring only one column is active at a time; ±24 mA drive handles 20-mA LED segments directly. |
Use Scenario: Decoding 3-bit chip-select lines for peripheral ICs (e.g., ADCs, DACs, EEPROMs) in an MCU-based data acquisition system. IC Role / Device Role / Timing Role: Address-space partitioner; maps microcontroller address bits A0–A2 to discrete peripheral enables. Use Value: Reduces GPIO count vs individual enables; 5.8 ns delay avoids wait-state insertion in 50-MHz bus timing. |
| Industrial I/O Expander | Factory Automation Logic Router |
|
Use Scenario: Enabling/disabling up to eight sensor inputs (e.g., limit switches, photoelectric sensors) based on PLC command word. IC Role / Device Role / Timing Role: Digital multiplexer controller; uses G1 as master enable and A/B/C as channel selector. Use Value: Simplifies firmware by replacing eight discrete enable lines with three address + one global enable. |
Use Scenario: Routing control signals from a central motion controller to eight servo drives in synchronized packaging machinery. IC Role / Device Role / Timing Role: Signal distributor; G2A/G2B tied to safety interlock status, G1 to motion enable, A/B/C to axis ID. Use Value: Enables fail-safe shutdown (all outputs HIGH) when either G2A or G2B goes HIGH, meeting SIL-2 requirements. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar 3-to-8 decoder applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74HC138N | Wider VCC range (2 V–6 V), slower speed (24 ns @ 4.5 V), higher drive (±5.2 mA), non-5.5-V-tolerant inputs. | Suitable for 5-V-only systems; lacks 1.8-V compatibility and 5-V input tolerance. | Choose SN74HC138N only for legacy 5-V designs where speed and low-voltage operation are secondary. |
| 74LVT138PW | Higher speed (3.5 ns @ 3.3 V), 3.3-V-only supply (3–3.6 V), TTL-compatible inputs, higher ICC (30 mA typical). | Optimized for ultra-fast bus buffering; incompatible with 1.8-V logic and 5-V inputs. | Prefer 74LVT138PW only in high-frequency backplane applications requiring sub-4-ns timing. |
Compared with SN74HC138N and 74LVT138PW, SN74LVC138APWRG4 uniquely balances 1.65–3.6-V operation, 5.5-V input tolerance, and 5.8-ns speed-making it the only choice for mixed-voltage, space-constrained industrial designs requiring both flexibility and performance.
Availability
SN74LVC138APWRG4 is available at Aetrix Electronics and suitable for LED displays, factory automation controllers, and power infrastructure monitoring systems requiring stable component supply across extended temperature ranges and long production lifecycles.
Supply support for SN74LVC138APWRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of experience in high-reliability logic and interface solutions.
The SN74LVC138A product line delivers low-voltage, high-speed decoding for memory, I/O expansion, and signal routing in industrial, automotive, and communications equipment-designed for robustness, interoperability, and seamless integration into modern mixed-signal systems.
FAQ
What is the maximum clock frequency supported by SN74LVC138APWRG4 for reliable decoding?
The SN74LVC138APWRG4 does not operate on a clock; it is a combinational logic device. Its maximum usable switching rate is determined by propagation delay: at 3.3 V, tpd ≤ 5.8 ns implies a minimum input transition interval of ~12 ns, supporting effective address/data rates up to ~83 MHz in synchronous systems. SN74LVC138APWRG4 performance remains stable across its full –40°C to +85°C operating range.
Can SN74LVC138APWRG4 safely interface with a 5-V microcontroller output?
Yes. SN74LVC138APWRG4 inputs tolerate voltages up to 5.5 V regardless of VCC level, allowing direct connection to 5-V GPIOs without level-shifting circuitry. This is confirmed in the datasheet's "Recommended Operating Conditions" table (VI = 0 to 5.5 V) and "Features" list. SN74LVC138APWRG4 maintains full functionality and reliability under this condition.
What is the recommended bypass capacitor for SN74LVC138APWRG4?
A 0.1-µF ceramic capacitor placed as close as possible to the VCC (pin 16) and GND (pin 8) terminals is mandatory for stable operation. TI's datasheet Section 10 specifies this value and emphasizes proximity to minimize inductance. For systems with broadband noise, paralleling a 1-µF capacitor is acceptable-but the 0.1-µF unit must be nearest the IC. SN74LVC138APWRG4 exhibits low ICC (<10 µA), but transient current demands during output switching require low-ESL/ESR capacitance.
Does SN74LVC138APWRG4 support cascading for larger decoder configurations?
Yes. SN74LVC138APWRG4 supports cascading via its three enable inputs: G1 (active-high) and G2A/G2B (active-low) allow hierarchical expansion. Two devices can implement a 4-to-16 decoder; three devices yield 24-line decoding without external inverters. The datasheet's Functional Description (Section 8.1) explicitly confirms this capability, and the truth table (Table 2) shows enable-controlled output disable states essential for cascading.
Is SN74LVC138APWRG4 pin-compatible with other package variants of the same part number?
Yes. SN74LVC138APWRG4 (TSSOP-16) shares identical pinout with SN74LVC138AD (SOIC-16), SN74LVC138ADBR (SSOP-16), and SN74LVC138ADGVR (TVSOP-16), as verified in TI's Pin Configuration and Functions section (page 3). All variants use the same 16-pin assignment: G2A(1), G2B(2), G1(3), C(4), B(5), A(6), Y7(7), GND(8), Y6(9), Y5(10), Y4(11), Y3(12), Y2(13), Y1(14), Y0(15), VCC(16). SN74LVC138APWRG4 maintains full functional and timing equivalence across packages.
SN74LVC138APWRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVC
- Package/Case:
- 16-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 3:8
- Independent Circuits:
- 1
- Current - Output High, Low:
- 24mA, 24mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 1.65V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-TSSOP
SN74LVC138APWRG4 FAQ
1.How can I place an order for SN74LVC138APWRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LVC138APWRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
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The price and inventory of SN74LVC138APWRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LVC138APWRG4 is usually 5 days.
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5.How can I obtain technical support or documentation for SN74LVC138APWRG4?
For technical support, including SN74LVC138APWRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LVC138APWRG4 requirements.
6.How does Aetrix verify that SN74LVC138APWRG4 is sourced from the original manufacturer or authorized distributors?
All SN74LVC138APWRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LVC138APWRG4 meets industry standards.
7.What is the process for return or replacement of SN74LVC138APWRG4?
All SN74LVC138APWRG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74LVC138APWRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LVC138APWRG4 part is unused and in its original packaging.
Return procedure for SN74LVC138APWRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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