Texas Instruments SN74LVC157ARGYRG4
- Part No.:
- SN74LVC157ARGYRG4
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 16-VFQFN Exposed Pad
- Datasheet:
-
SN74LVC157ARGYRG4.pdf
- Description:
- IC MULTIPLEXER 4 X 2:1 16VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:3,389
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74LVC157ARGYRG4 from Texas Instruments is a quadruple 2-line to 1-line data selector/multiplexer in a 16-pin VQFN (RGY) package, operating from 1.65V to 3.6V supply, with 5.2ns max propagation delay at 3.3V, 5.5V-tolerant inputs, and –40°C to 85°C temperature range. It routes four independent 2:1 data paths under common address (A/B) and strobe (G) control for bus selection and signal routing in low-voltage digital systems.
For engineers reviewing the SN74LVC157ARGYRG4 datasheet, SN74LVC157ARGYRG4 pinout, SN74LVC157ARGYRG4 application, or SN74LVC157ARGYRG4 equivalent, this page delivers verified electrical specs, thermal metrics, functional mode truth table, real-world layout guidance, and validated alternative options - all aligned to TI's SCAS292S production data sheet (December 2024 revision).
Technical Context
The SN74LVC157ARGYRG4 implements true (non-inverting) data selection logic with a common active-low output strobe (G) and shared address select (A/B). When G is high, all four Y outputs are forced low regardless of A/B or input states; when G is low, each Yn selects between An and Bn based on A/B level. Inputs tolerate up to 5.5V, enabling safe interfacing with 5V logic in mixed-voltage systems.
Its CMOS design supports rail-to-rail output swing (VOH ≥ VCC–0.2V, VOL ≤ 0.3V at 3.3V), exhibits low dynamic power (Cpd = 16pF at 3.3V), and maintains stable timing across –40°C to 85°C with tpd ≤ 5.2ns (3.3V) and tsk(o) ≤ 1.5ns. The RGY package features an exposed thermal pad (recommended tied to GND) and MSL Level-2 moisture sensitivity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65V to 3.6V - Enables direct integration into 1.8V, 2.5V, and 3.3V logic domains without level shifters. |
| Max Propagation Delay | 5.2ns at VCC = 3.3V - Supports >100MHz data switching in high-speed bus multiplexing applications. |
| Input Voltage Tolerance | Up to 5.5V - Allows safe connection to legacy 5V peripherals without external clamping or translation. |
| Operating Temperature | –40°C to +85°C - Qualified for industrial-grade embedded control and communications equipment. |
| Output Drive Strength | ±24mA at VCC = 3.0V - Sufficient to drive multiple LVC/LVT loads or short PCB traces without buffering. |
| Power Dissipation Cap | 500mW at TA ≤ 125°C - Supported by RGY package's 87.1°C/W junction-to-ambient thermal resistance. |
| ESD Robustness | ±2000V HBM, ±1000V CDM - Meets JEDEC JESD22-A114 and JESD22-C101 for reliable manufacturing handling. |
Pinout & Package
VQFN-16 (RGY) package: 4mm × 3.5mm body, 0.5mm pitch, exposed thermal pad (pin 17, recommended connected to GND). RoHS-compliant, NIPDAU lead finish, MSL Level-2 (260°C, 1 year floor life).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1 (A/B) | Address select input | Common control for all four 2:1 channels: selects A-input (low) or B-input (high) for each Y-output. |
| 2 (1A), 3 (1B), 4 (1Y) | Channel 1 data inputs / output | First independent 2:1 path; 1Y = A/B ? 1A : 1B when G = low. |
| 5 (2A), 6 (2B), 7 (2Y) | Channel 2 data inputs / output | Second independent 2:1 path; identical logic to Channel 1. |
| 8 (GND) | Ground reference | Primary return path for all I/O and internal logic; must be low-impedance. |
| 9 (3Y), 10 (3B), 11 (3A) | Channel 3 data output / inputs | Third independent 2:1 path; 3Y reflects selected input only when G = low. |
| 12 (4Y), 13 (4B), 14 (4A) | Channel 4 data output / inputs | Fourth independent 2:1 path; fully synchronous with other channels. |
| 15 (G) | Active-low output strobe | Global enable: G = high forces all Y-outputs low; G = low enables data routing per A/B. |
| 16 (VCC) | Positive supply | Single 1.65–3.6V rail powers all logic; requires local 0.1µF bypass capacitor adjacent to pin. |
Key Features
| Feature | Design Value |
|---|---|
| 5.5V-tolerant inputs | Enables direct interface with 5V microcontrollers or sensors while powered from 3.3V or lower rails. |
| Low propagation delay | 5.2ns max at 3.3V ensures minimal timing skew across all four channels in high-speed data routing. |
| Output ground bounce & undershoot control | Typical VOLP < 0.8V and VOHV > 2V at 3.3V reduce signal integrity risk in dense PCB layouts. |
| Latch-up immunity | Exceeds 250mA per JESD17 - prevents destructive latch-up during transient overvoltage events. |
| Thermal pad support | Exposed pad in RGY package lowers θJA to 87.1°C/W, improving power handling and long-term reliability. |
Applications
| Industrial Bus Multiplexing | FPGA I/O Expansion |
|---|---|
Use Scenario: Selecting between two sensor data streams (e.g., primary/backup temperature sensors) feeding a single ADC input in a PLC module. IC Role / Device Role / Timing Role: Quad 2:1 data selector providing synchronized channel selection with sub-6ns delay and glitch-free output enable via G pin. Use Value: Eliminates need for four discrete analog switches; reduces board space and improves timing consistency across channels. |
Use Scenario: Routing configuration data from dual flash memory banks to an FPGA JTAG or configuration port during boot. IC Role / Device Role / Timing Role: Logic-level multiplexer enabling failover or version-select capability without FPGA reconfiguration. Use Value: Provides hardware-controlled, zero-latency memory bank selection with 5.5V-tolerant inputs compatible with standard SPI flash voltage levels. |
| Low-Voltage Microcontroller Peripherals | Mixed-Voltage Signal Routing |
Use Scenario: Sharing a single UART TX line between two MCU peripherals (e.g., GPS and BLE module) in a wearable device. IC Role / Device Role / Timing Role: Bidirectional-capable (input-only) data selector managing TX line arbitration under firmware control. Use Value: Avoids software-based time-division multiplexing; guarantees deterministic signal routing with no CPU overhead. |
Use Scenario: Interfacing a 5V legacy display controller to a 3.3V SoC using shared data/address lines. IC Role / Device Role / Timing Role: Voltage-tolerant multiplexer isolating 5V signals from 3.3V domain while preserving logic levels. Use Value: Removes requirement for discrete level translators on each data line, cutting BOM cost and layout complexity. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 2:1 multiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC157ADG4 | SOIC-16 package (9.9mm × 6mm), higher θJA (118.1°C/W), same electrical specs and pinout. | Better suited for through-hole prototyping or legacy board designs requiring D-package footprint. | Select when manual soldering, thermal margin >85°C is not required, or existing SOIC land pattern exists. |
| SN74LV157ADR | LV-family variant: 2.0–5.5V supply range, slower tpd (7.4ns min at 3.3V), different input thresholds. | Compatible with 5V-only systems but lacks 5.5V-tolerant inputs at 1.8V operation; not drop-in for LVC-level designs. | Choose only if system operates above 2.0V and 5.5V tolerance is unnecessary; verify VIH/VIL compatibility. |
Compared with SN74LVC157ADG4 and SN74LV157ADR, the SN74LVC157ARGYRG4 offers superior thermal performance (87.1°C/W vs. 118.1°C/W), smallest footprint (4mm × 3.5mm), and guaranteed 5.5V input tolerance across its full 1.65–3.6V supply range - making it optimal for space-constrained, mixed-voltage industrial PCBs.
Availability
SN74LVC157ARGYRG4 is available at Aetrix Electronics and suitable for industrial automation, FPGA configuration management, low-power wearable peripherals, and mixed-voltage signal routing requiring stable component supply, consistent parametric performance, and long-term manufacturability.
Supply support for SN74LVC157ARGYRG4 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader delivering analog, embedded processing, and connectivity solutions with emphasis on reliability, precision, and energy efficiency.
The SN74LVC157ARGYRG4 belongs to TI's LVC (Low-Voltage CMOS) logic family, engineered for high-speed, low-power operation in 1.65–3.6V systems where signal integrity, voltage translation, and compact packaging are critical.
FAQ
What is the maximum clock/data rate supported by SN74LVC157ARGYRG4?
The SN74LVC157ARGYRG4 has a maximum propagation delay of 5.2ns at 3.3V, supporting data switching frequencies up to ~100MHz in well-designed PCB layouts. Real-world usable rate depends on load capacitance, trace length, and signal integrity margins - TI recommends limiting fan-out to ≤10 LVC loads and keeping traces under 2 inches for reliable 50MHz+ operation. The SN74LVC157ARGYRG4 is not a clocked device but a combinatorial multiplexer, so its speed is governed by tpd, not clock frequency.
Can SN74LVC157ARGYRG4 interface directly with 5V logic devices?
Yes. The SN74LVC157ARGYRG4 inputs are 5.5V-tolerant across its entire 1.65–3.6V supply range, allowing direct connection to 5V outputs without external level-shifting components. Outputs swing rail-to-rail (VOH ≥ VCC–0.2V, VOL ≤ 0.3V), so driving 5V-tolerant inputs is safe, but driving standard 5V TTL inputs may require verification of VIH/VIL thresholds. The SN74LVC157ARGYRG4 is commonly used in mixed 3.3V/5V systems for exactly this purpose.
How should the thermal pad on the RGY package of SN74LVC157ARGYRG4 be handled?
The exposed thermal pad on the SN74LVC157ARGYRG4 RGY package (pin 17) must be soldered to a PCB copper pour connected to GND for optimal thermal performance. TI specifies that connecting it to GND reduces θJA from 87.1°C/W to lower effective values and improves reliability under sustained load. Leaving it floating degrades thermal dissipation and is not recommended. No signal or supply other than GND should be connected to the pad.
Is SN74LVC157ARGYRG4 pin-compatible with other packages in the SN74LVC157A family?
Yes - the SN74LVC157ARGYRG4 shares identical pin numbering and function mapping with all other SN74LVC157A variants (e.g., D, DB, PW, NS packages), per TI's Pin Configuration and Functions documentation. All 16-pin versions implement the same logic diagram, truth table, and electrical behavior. However, mechanical dimensions, thermal resistance, and moisture sensitivity differ - the SN74LVC157ARGYRG4 uses VQFN (RGY) with MSL Level-2, unlike SOIC (D) which is MSL Level-1.
What happens to outputs when the G (strobe) pin is high?
When the G pin of the SN74LVC157ARGYRG4 is driven high, all four Y outputs (1Y–4Y) are forced low, regardless of the states of A/B, 1A–4A, or 1B–4B inputs. This active-low strobe provides synchronous disable capability for bus isolation or power sequencing. The SN74LVC157ARGYRG4 does not enter high-impedance (tri-state) mode - outputs are actively driven low, ensuring defined logic levels during disable.
SN74LVC157ARGYRG4 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVC
- Package/Case:
- 16-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Discontinued at Digi-Key
- Type:
- Multiplexer
- Circuit:
- 4 x 2:1
- Independent Circuits:
- 1
- Current - Output High, Low:
- 24mA, 24mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 2V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 16-VQFN (4x3.5)
SN74LVC157ARGYRG4 FAQ
1.How can I place an order for SN74LVC157ARGYRG4 through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LVC157ARGYRG4 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LVC157ARGYRG4 reliable?
The price and inventory of SN74LVC157ARGYRG4 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LVC157ARGYRG4 is usually 5 days.
3.What payment methods are accepted for SN74LVC157ARGYRG4?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LVC157ARGYRG4 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LVC157ARGYRG4?
SN74LVC157ARGYRG4 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LVC157ARGYRG4 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LVC157ARGYRG4?
For technical support, including SN74LVC157ARGYRG4 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LVC157ARGYRG4 requirements.
6.How does Aetrix verify that SN74LVC157ARGYRG4 is sourced from the original manufacturer or authorized distributors?
All SN74LVC157ARGYRG4 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LVC157ARGYRG4 meets industry standards.
7.What is the process for return or replacement of SN74LVC157ARGYRG4?
All SN74LVC157ARGYRG4 units undergo pre-shipment inspection (PSI). If there is an issue with SN74LVC157ARGYRG4, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LVC157ARGYRG4 part is unused and in its original packaging.
Return procedure for SN74LVC157ARGYRG4:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74LVC157ARGYRG4 Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
