Texas Instruments SN74LVC1G126DCKT
- Part No.:
- SN74LVC1G126DCKT
- Manufacturer:
- Texas Instruments
- Package:
- 5-TSSOP, SC-70-5, SOT-353
- Datasheet:
-
SN74LVC1G126DCKT.pdf
- Description:
- IC BUF NON-INVERT 5.5V SC70-5
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74LVC1G126 from Texas Instruments is a single-channel 3-state bus buffer gate used for signal isolation and controlled data routing in low-voltage digital systems. It features true (non-inverting) logic, ±24mA output drive at 3.3V, 3.7ns maximum propagation delay at 3.3V/CL=15pF, and operates across 1.65V–5.5V supply range - enabling use in mixed-voltage interfaces such as FPGA I/O expansion or microcontroller peripheral control.
For engineers reviewing the SN74LVC1G126 datasheet, SN74LVC1G126 pinout, SN74LVC1G126 application, or SN74LVC1G126 equivalent, key selection criteria include its over-voltage tolerant inputs (up to 5.5V), Ioff support for live insertion, balanced CMOS 3-state outputs, and NanoFree™ SC70-5 package compatibility with high-density PCB layouts.
Technical Context
The SN74LVC1G126 implements a non-inverting buffer with active-high output enable (OE), where Y = A when OE = HIGH and Y = high-impedance when OE = LOW. Its input structure supports voltage translation: inputs accept up to 5.5V regardless of VCC, enabling interfacing between 5V legacy logic and 1.8V/2.5V/3.3V core logic.
It uses standard CMOS input gates with clamped negative ESD diodes and no positive clamp, requiring fast input transitions (≤5 ns/V at 5V) to prevent oscillation. The balanced 3-state output stage provides symmetrical sourcing/sinking capability (±24mA at 3.3V), and Ioff functionality ensures zero current flow when VCC = 0V - critical for hot-swap and partial-power-down systems.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Supply Voltage Range | 1.65V to 5.5V - supports operation across 1.8V, 2.5V, 3.3V, and 5V logic domains |
| Max Propagation Delay | 3.7ns at VCC = 3.3V, CL = 15pF - enables >200MHz data rate in point-to-point routing |
| Output Drive Strength | ±24mA at VCC = 3.3V - sufficient to drive multiple LVC loads or moderate capacitive loads without external buffering |
| Input Voltage Tolerance | Up to 5.5V independent of VCC - allows safe interfacing with 5V signals while powered from lower VCC |
| IOFF Current | ±10μA max at VCC = 0V - prevents back-drive and enables live insertion in powered-backplane systems |
| ESD Rating (HBM) | 2000V - meets industrial-grade robustness requirements per ANSI/ESDA/JEDEC JS-001 |
| Operating Temperature | –40°C to +125°C - qualified for automotive under-hood and industrial control environments |
Pinout & Package
SN74LVC1G126DCKT uses the DCK (SC-70-5) package: 2.0mm × 2.1mm body size, 5-pin surface-mount, lead-free and RoHS-compliant. Pin 1 is A (data input), Pin 2 is GND, Pin 3 is Y (3-state output), Pin 4 is OE (active-high output enable), Pin 5 is VCC.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A | Data input | True logic input; accepts voltages up to 5.5V regardless of VCC level |
| GND | Ground reference | Return path for all internal circuitry and output current sinking |
| Y | 3-state buffered output | Drives HIGH/LOW or enters high-Z when OE = LOW; supports bus sharing |
| OE | Output enable (active-high) | Controls Y state: HIGH enables pass-through (Y = A), LOW forces high-impedance |
| VCC | Power supply | Supplies core logic and output drivers; sets VOH/VOL thresholds and timing behavior |
Key Features
| Feature | Design Value |
|---|---|
| Over-voltage tolerant inputs | Accepts 0–5.5V input signals even when VCC = 1.65V - eliminates level-shifters in mixed-voltage I/O |
| IOFF partial power-down | Blocks current flow through I/O pins when VCC = 0V - enables safe hot-plug into live backplanes |
| Balanced CMOS 3-state outputs | Sources and sinks ±24mA symmetrically at 3.3V - ensures clean edges into light loads and avoids shoot-through |
| NanoFree™ SC-70 package | 2.0mm × 2.1mm footprint - saves board space in portable, wearables, and dense FPGA interface designs |
| Wide temperature range | Specified from –40°C to +125°C - suitable for engine control units, motor drives, and outdoor infrastructure |
Applications
| Industrial Motor Control | FPGA I/O Expansion |
|---|---|
Use Scenario: Isolating encoder feedback signals and PWM outputs in servo drives with shared bus architecture. IC Role / Device Role / Timing Role: Bus buffer with 3-state control enables dynamic reconfiguration of sensor/data lines without contention. Use Value: ±24mA drive strength sustains signal integrity across noisy motor-control PCB traces; Ioff prevents back-drive during power sequencing. |
Use Scenario: Extending limited FPGA GPIOs to interface with multiple peripherals (ADCs, DACs, sensors) via shared data bus. IC Role / Device Role / Timing Role: Single-channel direction-controlled buffer manages unidirectional data flow from FPGA to external devices. Use Value: 3.7ns tpd ensures timing closure in 100+ MHz parallel interfaces; 5.5V-tolerant inputs simplify connection to legacy 5V peripherals. |
| Automotive Body Control Module | High-Speed Data Acquisition |
Use Scenario: Level-shifting and isolating LIN transceiver control signals in battery-powered BCM sub-systems. IC Role / Device Role / Timing Role: Signal conditioner that translates 3.3V MCU outputs to 5V-compatible control lines while supporting hot-swap. Use Value: Ioff and –40°C to +125°C rating ensure reliability during vehicle start-stop cycles and under-hood thermal stress. |
Use Scenario: Buffering trigger and clock distribution lines in multi-channel oscilloscope front-end ASIC interfaces. IC Role / Device Role / Timing Role: Low-skew, low-capacitance buffer preserves edge fidelity on sampling clocks and strobes. Use Value: 4pF input capacitance minimizes loading on high-frequency clock trees; 2000V HBM ESD withstands lab handling and probe contact. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G125DCKT | Inverting logic (Y = NOT A); identical electrical specs, package, and pinout | Requires logic inversion in signal path; unsuitable where polarity must be preserved | Select SN74LVC1G125DCKT only when system-level inversion is acceptable or required |
| NC7SZ126P5X | Same function but rated only to 85°C ambient; lower ESD rating (1500V HBM); different thermal resistance (RθJA = 390°C/W) | Not qualified for automotive or extended-temperature industrial use | Prefer NC7SZ126P5X only for cost-sensitive commercial-grade applications below 85°C |
Compared with SN74LVC1G126DCKT, SN74LVC1G125DCKT offers identical performance with inverted logic - useful for complementary signaling but incompatible in non-inverting paths; NC7SZ126P5X trades temperature range and ESD robustness for lower cost, limiting suitability to benign environments.
Availability
SN74LVC1G126DCKT is available at Aetrix Electronics and suitable for industrial motor control, FPGA I/O expansion, automotive body electronics, high-speed data acquisition, and embedded sensor interface applications requiring stable component supply, long-term lifecycle assurance, and traceable sourcing.
Supply support for SN74LVC1G126DCKT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of experience in high-reliability industrial and automotive IC design.
The SN74LVC1G126 belongs to TI's LVC (Low-Voltage CMOS) logic family, engineered for low-power, high-speed interoperability across mixed-voltage digital systems - particularly targeting space-constrained, thermally demanding, and safety-critical embedded interfaces.
FAQ
What is the maximum input voltage the SN74LVC1G126DCKT can tolerate?
The SN74LVC1G126DCKT accepts input voltages up to 5.5V on A and OE pins, regardless of VCC level - a feature known as over-voltage tolerance. This allows direct interfacing with 5V signals while operating from 1.65V–5.5V supplies. Exceeding 5.5V violates Absolute Maximum Ratings and risks permanent damage.
Does the SN74LVC1G126DCKT support hot-swap or live insertion?
Yes, the SN74LVC1G126DCKT supports live insertion via its Ioff feature: when VCC = 0V, all I/O pins enter a high-impedance state with leakage ≤±10μA, preventing back-drive into powered systems. This makes SN74LVC1G126DCKT suitable for modular backplanes and hot-pluggable modules.
What is the recommended bypass capacitor for SN74LVC1G126DCKT?
A 0.1μF ceramic capacitor placed as close as possible between VCC and GND pins is recommended for SN74LVC1G126DCKT. For improved noise suppression across frequencies, TI recommends paralleling it with a 1μF capacitor. Layout must minimize loop inductance using short, wide traces and a solid ground plane.
Can SN74LVC1G126DCKT drive a 50pF load while meeting timing specs?
Yes - SN74LVC1G126DCKT is characterized up to 50pF load capacitance in its switching specifications (e.g., tpd ≤4.7ns at VCC = 3.3V, –40°C to +125°C). For loads exceeding 50pF, TI recommends adding a series damping resistor near the output to suppress ringing and maintain signal integrity.
Is SN74LVC1G126DCKT pin-compatible with other SC-70-5 logic buffers?
SN74LVC1G126DCKT shares the SC-70-5 (DCK) package and pinout (A-GND-Y-OE-VCC) with functionally similar TI parts like SN74LVC1G125DCKT and SN74LVC1G07DCKT, but not with non-TI SC-70-5 buffers unless explicitly verified. Always confirm pin mapping and logic function before substitution.
SN74LVC1G126DCKT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVC
- Package/Case:
- 5-TSSOP, SC-70-5, SOT-353
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SC-70-5
SN74LVC1G126DCKT FAQ
1.How can I place an order for SN74LVC1G126DCKT through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LVC1G126DCKT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LVC1G126DCKT reliable?
The price and inventory of SN74LVC1G126DCKT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LVC1G126DCKT is usually 5 days.
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Once your SN74LVC1G126DCKT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LVC1G126DCKT?
For technical support, including SN74LVC1G126DCKT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LVC1G126DCKT requirements.
6.How does Aetrix verify that SN74LVC1G126DCKT is sourced from the original manufacturer or authorized distributors?
All SN74LVC1G126DCKT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LVC1G126DCKT meets industry standards.
7.What is the process for return or replacement of SN74LVC1G126DCKT?
All SN74LVC1G126DCKT units undergo pre-shipment inspection (PSI). If there is an issue with SN74LVC1G126DCKT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LVC1G126DCKT part is unused and in its original packaging.
Return procedure for SN74LVC1G126DCKT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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