Texas Instruments SN74LVC1G126DRYR
- Part No.:
- SN74LVC1G126DRYR
- Manufacturer:
- Texas Instruments
- Package:
- 6-UFDFN
- Datasheet:
-
SN74LVC1G126DRYR.pdf
- Description:
- IC BUFFER NON-INVERT 5.5V 6SON
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74LVC1G126DRYR from Texas Instruments is a single-channel 3-state bus buffer gate in a 6-pin SON (DRY) package, supporting 1.65–5.5V supply operation, 3.7ns max propagation delay at 3.3V, ±24mA output drive, and Ioff-enabled live insertion for industrial data acquisition and video infrastructure signal routing.
For engineers reviewing the SN74LVC1G126DRYR datasheet, SN74LVC1G126DRYR pinout, SN74LVC1G126DRYR application, or SN74LVC1G126DRYR equivalent, this page delivers verified electrical specs, thermal metrics, functional mode behavior, and real-world implementation guidance for high-speed digital interface design with voltage translation and bus isolation requirements.
Technical Context
The SN74LVC1G126DRYR implements a non-inverting true-buffer logic function with active-high output enable (OE), where Y = A when OE = HIGH and Y = high-impedance when OE = LOW. Its balanced CMOS 3-state outputs support bidirectional current sourcing/sinking up to ±24mA at 3.3V while maintaining rail-to-rail output swing (VOH ≥ VCC – 0.1V, VOL ≤ 0.55V).
It features over-voltage tolerant inputs (VI up to 5.5V independent of VCC), Ioff protection enabling partial power-down without back-drive damage, and input transition rate compliance down to 5 ns/V at 5V - ensuring robust operation across mixed-voltage systems and hot-swap environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65V to 5.5V - enables direct interfacing between 1.8V, 2.5V, 3.3V, and 5V logic domains with no level-shifter required. |
| tpd (max) | 3.7ns at VCC = 3.3V, CL = 15pF - supports >100MHz data rates in point-to-point digital links with tight timing margins. |
| Output Drive | ±24mA at VCC = 3V - sufficient to drive 50Ω transmission lines or multiple CMOS inputs without external buffering. |
| Ioff Leakage | ±10μA max at VI/VO = 5.5V - prevents current flow during power sequencing, enabling safe live insertion in backplane or modular systems. |
| Input Voltage Tolerance | Up to 5.5V regardless of VCC - allows 5V-tolerant inputs on 1.8V/2.5V-powered devices, simplifying mixed-supply board design. |
| Operating Temp | –40°C to +125°C - qualified for extended industrial and automotive under-hood applications requiring thermal resilience. |
| ICC (max) | 10μA - ultra-low static power enables battery-backed or always-on monitoring circuits with minimal quiescent drain. |
Pinout & Package
SN74LVC1G126DRYR uses a 1.45mm × 1.0mm 6-pin SON (Small Outline No-lead) package with wettable flank terminations for automated optical inspection (AOI). The DRY package has exposed thermal pad (pin 6 = VCC) and no internal die attach paddle connection - thermal resistance RθJA = 234°C/W.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| A | Data Input | True logic input; accepts voltages up to 5.5V and translates down to VCC - enables voltage-level agnostic signal injection. |
| OE | Output Enable (Active-High) | Controls 3-state output: HIGH enables buffer pass-through (Y = A); LOW forces high-impedance - used for bus arbitration and signal gating. |
| GND | Ground Reference | Primary return path for all currents; must be low-impedance and adjacent to VCC for stable switching and noise immunity. |
| Y | Buffered Output | Non-inverted, 3-state output with ±24mA drive capability; floats when OE = LOW - isolates downstream circuitry during standby. |
| VCC | Power Supply | Supplies core logic and output drivers; bypassing with 0.1μF capacitor near pin is mandatory for clean switching transients. |
| N.C. | No Connect | Pin 5 is unconnected internally - must remain unpopulated or left floating; no routing or soldering required. |
Key Features
| Feature | Design Value |
|---|---|
| NanoFree™ DRY package | 1.45mm × 1.0mm footprint with wettable flanks - reduces PCB area by >50% vs SOT-23 and enables AOI-compatible assembly. |
| Over-voltage tolerant inputs | Accepts 0–5.5V input signals regardless of VCC setting - eliminates need for external clamping diodes or level shifters in mixed-voltage buses. |
| Ioff partial-power-down | Blocks current flow between powered/unpowered sections when VCC = 0V - prevents back-driving and latch-up during hot-plug events. |
| Low propagation delay | 3.7ns max at 3.3V/15pF - meets setup/hold timing for FPGA I/O, microcontroller GPIO expansion, and high-speed serial link control paths. |
| ESD robustness | 2000V HBM, 1000V CDM - exceeds JEDEC JS-001/JS-002 requirements for manufacturing handling and field reliability. |
Applications
| Video Broadcasting Infrastructure | Military Radar Signal Conditioning |
|---|---|
|
Use Scenario: Routing uncompressed HD/SDI video clock and data signals between FPGA-based transcoders and distribution amplifiers in scalable IP broadcast platforms. IC Role / Device Role / Timing Role: Single-channel 3-state buffer isolating clock/data lanes during reconfiguration, preventing bus contention during hot-swap module replacement. Use Value: Enables seamless failover and firmware updates without interrupting video stream integrity - leveraging Ioff and 125°C operation for fanless chassis designs. |
Use Scenario: Interfacing ADC/DAC control lines and trigger signals between radar processor modules and RF front-end assemblies in airborne radar systems. IC Role / Device Role / Timing Role: Level-translating and isolating critical timing signals (e.g., sample clocks, sync pulses) across 1.8V processor and 3.3V analog subsystems. Use Value: Maintains signal fidelity under wide temperature swings (–40°C to +125°C) and ensures no back-drive during partial system power-down - meeting MIL-STD-810G environmental compliance. |
| Industrial Motor Control I/O Expansion | SSD Internal Bus Isolation |
|
Use Scenario: Buffering GPIO and status signals between microcontroller units and isolated gate drivers in high-voltage motor drives (e.g., HVAC compressors, EV traction inverters). IC Role / Device Role / Timing Role: Providing galvanically isolated signal conditioning via 3-state output enable, decoupling MCU timing from noisy power stage switching transients. Use Value: Reduces EMI-induced glitches on control lines using fast edge control (3.7ns tpd) and rail-to-rail VOH/VOL - improving PWM accuracy and fault response time. |
Use Scenario: Isolating NAND flash command/address/data buses from host controller in enterprise SSD modules during firmware updates or power-loss recovery sequences. IC Role / Device Role / Timing Role: Acting as a bi-directional bus keeper during suspend/resume cycles - holding bus state via high-Z output until host reasserts control. Use Value: Prevents data corruption during unexpected power loss by eliminating floating bus states - supported by Ioff and <10μA ICC for ultra-low standby leakage. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar bus buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G125DRYR | Inverting buffer (Y = NOT A) vs non-inverting; otherwise identical electrical specs, pinout, and package. | Requires logic inversion in signal path - unsuitable where polarity must be preserved (e.g., clock forwarding, address latching). | Select SN74LVC1G125DRYR only if system-level logic requires inversion; otherwise SN74LVC1G126DRYR is direct functional match. |
| SN74AUP1G126DBVR | Ultra-low-power variant (ICC < 0.9μA), slower tpd (6.1ns @ 3.3V), same 3-state function and 1.8–3.6V VCC range. | Better suited for battery-powered IoT sensors; not rated for 5V operation or 125°C - limits use in industrial/military contexts. | Choose SN74AUP1G126DBVR for energy-constrained portable devices; retain SN74LVC1G126DRYR for full-voltage-range, high-temp, or speed-critical designs. |
Compared with SN74LVC1G125DRYR and SN74AUP1G126DBVR, SN74LVC1G126DRYR uniquely balances 5V tolerance, 125°C rating, sub-4ns speed, and NanoFree packaging - making it optimal for space-constrained, thermally demanding, mixed-voltage digital interfaces where signal polarity integrity is essential.
Availability
SN74LVC1G126DRYR is available at Aetrix Electronics and suitable for industrial motor controls, video broadcasting infrastructure, military radar signal conditioning, and SSD internal bus isolation requiring stable component supply across extended temperature and voltage ranges.
Supply support for SN74LVC1G126DRYR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of expertise in high-reliability interface ICs for industrial, automotive, and aerospace markets.
The SN74LVC1G126DRYR belongs to TI's LVC (Low-Voltage CMOS) logic family, designed specifically for voltage translation, bus isolation, and signal integrity preservation in compact, thermally constrained digital systems.
FAQ
What is the maximum operating temperature for SN74LVC1G126DRYR?
The SN74LVC1G126DRYR is specified for continuous operation from –40°C to +125°C ambient temperature. This extended range is validated per JEDEC JESD22-A108 and supports deployment in under-hood automotive, industrial motor drives, and military radar enclosures without derating. Thermal performance is enhanced by the DRY package's 234°C/W junction-to-ambient resistance and exposed thermal pad layout.
Does SN74LVC1G126DRYR support 5V-tolerant inputs when powered at 1.8V?
Yes, SN74LVC1G126DRYR supports input voltages up to 5.5V regardless of VCC level - including when VCC = 1.8V. This over-voltage tolerance is achieved via internal protection circuitry without positive clamp diodes, enabling direct connection to 5V buses while operating from low-voltage rails. Input leakage remains ≤±5μA across the full range.
Can SN74LVC1G126DRYR be used for hot-swap applications?
Yes, SN74LVC1G126DRYR supports hot-swap via its Ioff feature: when VCC = 0V, all I/O pins enter high-impedance state with ≤±10μA leakage, preventing back-drive and current flow between powered and unpowered boards. This is explicitly tested per JESD78 Class II latch-up standards and validated for live insertion in modular telecom and test equipment.
What is the recommended bypass capacitor for SN74LVC1G126DRYR?
A 0.1μF ceramic capacitor placed as close as possible to the VCC pin (Pin 6) and GND (Pin 3) is mandatory for stable operation. TI recommends using X7R dielectric with ≤2mm trace length and low-inductance layout - verified to suppress switching noise and maintain <100mV ripple under 24mA load transients. For broadband noise suppression, add a parallel 1μF capacitor.
Is SN74LVC1G126DRYR pin-compatible with other packages in the same family?
No - SN74LVC1G126DRYR (6-pin SON) has different pin count and layout than DBV (5-pin SOT-23), DCK (5-pin SC70), or YZP (5-pin DSBGA) variants. While functional behavior is identical, mechanical compatibility requires redesign: DRY adds N.C. pin (Pin 5) and relocates VCC to Pin 6, altering PCB footprint and routing. Always verify land pattern against TI's SLMA001B mechanical drawing.
SN74LVC1G126DRYR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVC
- Package/Case:
- 6-UFDFN
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 1
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 32mA
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 6-SON (1.45x1)
SN74LVC1G126DRYR FAQ
1.How can I place an order for SN74LVC1G126DRYR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LVC1G126DRYR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LVC1G126DRYR reliable?
The price and inventory of SN74LVC1G126DRYR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LVC1G126DRYR is usually 5 days.
3.What payment methods are accepted for SN74LVC1G126DRYR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LVC1G126DRYR transactions.
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4.How is shipping managed for SN74LVC1G126DRYR?
SN74LVC1G126DRYR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LVC1G126DRYR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LVC1G126DRYR?
For technical support, including SN74LVC1G126DRYR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LVC1G126DRYR requirements.
6.How does Aetrix verify that SN74LVC1G126DRYR is sourced from the original manufacturer or authorized distributors?
All SN74LVC1G126DRYR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LVC1G126DRYR meets industry standards.
7.What is the process for return or replacement of SN74LVC1G126DRYR?
All SN74LVC1G126DRYR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LVC1G126DRYR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LVC1G126DRYR part is unused and in its original packaging.
Return procedure for SN74LVC1G126DRYR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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