Texas Instruments SN74LVC1G29DCTT
- Part No.:
- SN74LVC1G29DCTT
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 8-LSSOP, 8-MSOP (0.110", 2.80mm Width)
- Datasheet:
-
SN74LVC1G29DCTT.pdf
- Description:
- SN74LVC1G29 2-OF-3 DECODER/DEMUL
- Quantity:
- Payment:

- Shipping:

Inventory:1,250
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74LVC1G29DCTT from Texas Instruments is a single 2-of-3 decoder/demultiplexer IC operating from 1.65 V to 5.5 V, featuring 5.1 ns max propagation delay at 3.3 V, ±24 mA output drive, and Ioff support for live insertion and partial-power-down applications. It implements active-low enable logic with three outputs (Y0–Y2), used in address decoding, signal routing, and power sequencing in compact digital systems.
For engineers reviewing the SN74LVC1G29DCTT datasheet, SN74LVC1G29DCTT pinout, SN74LVC1G29DCTT application, or SN74LVC1G29DCTT equivalent, key selection criteria include VCC voltage range compatibility (1.65–5.5 V), low ICC (≤10 µA), Ioff-enabled back-drive protection, and DCT package thermal performance (θJA = 220°C/W).
Technical Context
This device implements a 2-input (A0, A1) + enable (G) logic decoder with three complementary outputs (Y0–Y2), where only one output goes low per valid input combination when G is low. Its architecture supports down-translation: inputs tolerate up to 5.5 V regardless of VCC, enabling mixed-voltage interface between 5-V legacy logic and lower-VCC subsystems.
The SN74LVC1G29DCTT integrates Ioff circuitry that disables outputs during power-down, preventing current backflow and enabling hot-plug capability. Its NanoFree™ DCT package uses the silicon die as the package body, eliminating bond wires and reducing parasitic inductance for improved signal integrity in high-speed switching.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - enables direct interfacing with 1.8-V, 2.5-V, 3.3-V, and 5-V logic families without level shifters. |
| tpd (Max) | 5.1 ns at VCC = 3.3 V, CL = 15 pF - ensures sub-6-ns timing margin for 100+ MHz clock domain control signals. |
| IOL / IOH | ±24 mA at VCC = 3.3 V - drives standard LVC loads, LED indicators, or small gate fanouts without external buffers. |
| Ioff Current | ±10 µA max - blocks current flow between powered and unpowered rails, critical for PCIe hot-swap and modular backplane designs. |
| Input Voltage Tolerance | Up to 5.5 V independent of VCC - allows safe connection to 5-V buses while VCC operates at 1.8 V or 2.5 V. |
| Power Consumption | 10 µA max ICC - supports ultra-low-quiescent-power modes in battery-backed or always-on monitoring circuits. |
| ESD Rating | HBM: 2000 V - meets industrial-grade robustness requirements for board-level handling and field deployment. |
Pinout & Package
DCT package: 8-pin small-outline package (SOIC-8 variant), 2.9 mm × 1.6 mm footprint, 1.3 mm max height, exposed pad not present, RoHS-compliant NiPdAu finish, MSL Level-1.
| Pin | Circuit Role | Design Meaning |
|---|---|---|
| 1 | G (Enable) | Active-low enable input; when low, decoder activates; when high, all outputs forced high - used for hierarchical enable tree control. |
| 2 | A0 (Address 0) | LSB address input; selects Y0/Y1/Y2 output state in conjunction with A1 - forms binary-coded selection of one of three paths. |
| 3 | Y0 (Output 0) | Active-low decoded output; low only when G = L, A1 = L, A0 = X - drives reset lines, chip-selects, or LED anodes directly. |
| 4 | GND | Ground reference for logic and power domains - must be low-impedance connection to minimize ground bounce (VOLP < 0.8 V). |
| 5 | Y2 (Output 2) | Active-low decoded output; low only when G = L, A1 = H, A0 = H - routes control signals to third peripheral in tri-state resource allocation. |
| 6 | A1 (Address 1) | MSB address input; determines which of Y0/Y1/Y2 asserts low with A0 - enables 2-bit address decoding for memory-mapped peripherals. |
| 7 | Y1 (Output 1) | Active-low decoded output; low only when G = L, A1 = H, A0 = L - controls enable/disable of secondary subsystems like sensor interfaces or DACs. |
| 8 | VCC | Supply voltage input; powers internal logic and output drivers - decoupling capacitor (0.1 µF) required within 3 mm for stable 5.1 ns switching. |
Key Features
| Feature | Design Value |
|---|---|
| NanoFree™ DCT package | Die-as-package construction eliminates bond wires, reduces package inductance by >40%, and improves thermal resistance (θJA = 220°C/W). |
| Ioff partial-power-down support | Enables live insertion into powered backplanes and prevents damaging current flow when VCC is off or ramping - essential for modular compute cards. |
| 5-V tolerant inputs | Accepts 0–5.5 V input signals regardless of VCC setting (1.65–5.5 V), simplifying interconnection with legacy 5-V microcontrollers or FPGAs. |
| Low dynamic ground bounce | VOLP < 0.8 V at VCC = 3.3 V ensures noise margins remain intact during simultaneous output switching in dense PCB layouts. |
| High-output drive strength | 24 mA sink/source capability allows direct driving of LEDs, optocouplers, or multiple 74LVC inputs without buffering - reduces BOM count. |
Applications
| Industrial Sensor Hub | Portable Medical Device |
|---|---|
Use Scenario: Selecting one of three analog front-end channels (ECG, SpO₂, temperature) for ADC sampling in a wearable monitor. IC Role / Device Role / Timing Role: 2-of-3 decoder enabling time-multiplexed analog path selection under MCU GPIO control. Use Value: Eliminates mechanical switches or larger multiplexers; 5.1 ns tpd ensures no timing skew between channel enable and ADC start pulse. |
Use Scenario: Routing power-enable signals to three isolated subsystems (display backlight, wireless transceiver, data logger) based on mode selection. IC Role / Device Role / Timing Role: Low-power demultiplexer controlling PMIC enable inputs with precise sequencing. Use Value: 10 µA ICC and Ioff support extend battery life and prevent cross-talk during sleep/wake transitions. |
| Automotive Body Control Module | Industrial PLC I/O Expansion |
Use Scenario: Decoding CAN message ID bits to activate one of three lamp driver ICs (headlight, brake, turn signal) in a lighting controller. IC Role / Device Role / Timing Role: Address decoder translating 2-bit command fields into discrete output enables. Use Value: 5.5-V input tolerance accepts raw CAN transceiver outputs; ±24 mA drive directly sources lamp driver enable pins. |
Use Scenario: Expanding GPIO count of a microcontroller to manage eight discrete I/O points using three SN74LVC1G29DCTT devices in parallel. IC Role / Device Role / Timing Role: Compact 3-output demux providing additional addressable control lines for relay banks or status LEDs. Use Value: DCT package (2.9 × 1.6 mm) saves >60% board area vs. SOIC-14 alternatives; RoHS/MSL-1 compliance supports automated assembly. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar decoder/demultiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G139DCUR | 2-line-to-4-line decoder with dual enable (G1, G2); identical VCC range and Ioff but adds second enable input. | Supports dual-control enable schemes (e.g., global + local), whereas SN74LVC1G29DCTT uses single-G enable. | Select SN74LVC1G139DCUR when hierarchical enable logic or 4-output expansion is required; DCU package has higher θJA (227°C/W) than DCT. |
| 74LVC1G238GW,125 | 2-of-4 decoder in SOT363 (6-pin) package; lacks Ioff, max VCC = 5.5 V, but offers 4 outputs instead of 3. | Requires external pull-ups for unused outputs; no live-insertion support due to missing Ioff circuitry. | Choose 74LVC1G238GW,125 only for cost-sensitive, non-hot-swap applications needing four outputs; DCT package provides superior thermal performance. |
Compared with SN74LVC1G29DCTT, SN74LVC1G139DCUR adds flexibility via dual enable but increases layout complexity, while 74LVC1G238GW,125 trades Ioff safety and thermal efficiency for output count - SN74LVC1G29DCTT remains optimal for space-constrained, hot-plug-capable 3-output decoding.
Availability
SN74LVC1G29DCTT is available at Aetrix Electronics and suitable for industrial sensor hubs, portable medical devices, automotive lighting controllers, and PLC I/O expansion requiring stable component supply across extended temperature ranges (–40°C to +85°C).
Supply support for SN74LVC1G29DCTT includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with over 50 years of innovation in high-reliability logic and interface solutions.
The SN74LVC1G29DCTT belongs to TI's LVC logic family, designed specifically for low-voltage, high-speed, mixed-signal system interfacing in space-constrained industrial and portable applications.
FAQ
What is the maximum operating frequency supported by SN74LVC1G29DCTT?
The SN74LVC1G29DCTT does not specify a maximum clock frequency, as it is a combinational logic device without internal clocking. Its 5.1 ns propagation delay at 3.3 V supports reliable operation in systems with input signal edges faster than ~100 MHz, provided setup/hold times are met and load capacitance stays ≤15 pF.
Can SN74LVC1G29DCTT be used with a 1.8-V supply while interfacing to 5-V microcontroller GPIOs?
Yes. The SN74LVC1G29DCTT supports VCC as low as 1.65 V and accepts input voltages up to 5.5 V independent of VCC. When powered at 1.8 V, its inputs safely interface with 5-V MCU outputs, and its outputs swing rail-to-rail (0 V to 1.8 V), making level translation unnecessary for enable/address signals.
Does SN74LVC1G29DCTT require external pull-up or pull-down resistors on unused inputs?
Yes. Per TI's recommended operating conditions, all unused inputs (including A0, A1, and G) must be held at VCC or GND to prevent floating states that cause increased ICC, oscillation, or undefined outputs. TI recommends tying unused inputs directly to VCC or GND - no resistor values are specified because CMOS inputs draw negligible current.
How does the Ioff feature of SN74LVC1G29DCTT protect system-level designs?
The Ioff feature disables all outputs when VCC = 0 V, blocking current flow between powered and unpowered sections of a system. In SN74LVC1G29DCTT, this prevents back-driving damage during hot-swap events, supports partial power-down in battery-powered systems, and eliminates leakage paths in multi-rail FPGA or ASIC interfaces - verified per JESD78 Class II latch-up testing.
Is the DCT package of SN74LVC1G29DCTT compatible with standard SOIC-8 reflow profiles?
Yes. The DCT package (SM8) is JEDEC MS-187 registered and rated MSL Level-1 (unlimited floor life), with peak reflow temperature up to 260°C. Its 2.9 mm × 1.6 mm footprint and 1.3 mm height match standard SOIC-8 stencil and placement tooling, enabling drop-in use in existing SOIC-8 assembly lines without process changes.
SN74LVC1G29DCTT Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVC
- Package/Case:
- 8-LSSOP, 8-MSOP (0.110", 2.80mm Width)
- Packaging:
- Bulk
- Product Status:
- Obsolete
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 2:3
- Independent Circuits:
- 1
- Current - Output High, Low:
- 32mA, 32mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- SM8
SN74LVC1G29DCTT FAQ
1.How can I place an order for SN74LVC1G29DCTT through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LVC1G29DCTT on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LVC1G29DCTT reliable?
The price and inventory of SN74LVC1G29DCTT are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LVC1G29DCTT is usually 5 days.
3.What payment methods are accepted for SN74LVC1G29DCTT?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LVC1G29DCTT transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LVC1G29DCTT?
SN74LVC1G29DCTT orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LVC1G29DCTT order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LVC1G29DCTT?
For technical support, including SN74LVC1G29DCTT datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LVC1G29DCTT requirements.
6.How does Aetrix verify that SN74LVC1G29DCTT is sourced from the original manufacturer or authorized distributors?
All SN74LVC1G29DCTT products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LVC1G29DCTT meets industry standards.
7.What is the process for return or replacement of SN74LVC1G29DCTT?
All SN74LVC1G29DCTT units undergo pre-shipment inspection (PSI). If there is an issue with SN74LVC1G29DCTT, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LVC1G29DCTT part is unused and in its original packaging.
Return procedure for SN74LVC1G29DCTT:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74LVC1G29DCTT Tags
-
SN74HC138DR
Texas Instruments

-
TC7SB3157CFU,LF(CT
Toshiba Semiconductor and Storage

-
74CBTLV3257PW,118
Nexperia USA Inc.
-
SN74CBTLV3257PWR
Texas Instruments

-
74CBTLV3257GUX
Nexperia USA Inc.

-
74HC154BQ,118
Nexperia USA Inc.

-
P3S0200GMX
NXP USA Inc.

-
SN74CB3Q3245PWR
Texas Instruments
-
SN74CB3Q3257RGYR
Texas Instruments

-
TCA9543APWR
Texas Instruments
-
TCA9546APWR
Texas Instruments

-
SN74HC138N
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…
