Texas Instruments SN74LVC1G29YEPR
- Part No.:
- SN74LVC1G29YEPR
- Manufacturer:
- Texas Instruments
- Category:
- Signal Switches, Multiplexers, Decoders
- Package:
- 8-VFSOP (0.091", 2.30mm Width)
- Datasheet:
-
SN74LVC1G29YEPR.pdf
- Description:
- IC DECODER/DEMUX 1X2:3 8VSSOP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SN74LVC1G29YEPR from Texas Instruments is a single 2-of-3 decoder/demultiplexer IC operating from 1.65 V to 5.5 V, featuring 5.1 ns max propagation delay at 3.3 V, ±24-mA output drive, and Ioff support for live insertion and partial-power-down applications. It decodes two address inputs (A0, A1) into three active-low outputs (Y0–Y2) under enable control (G), used in address decoding and signal routing in space-constrained logic systems.
For engineers reviewing the SN74LVC1G29YEPR datasheet, SN74LVC1G29YEPR pinout, SN74LVC1G29YEPR application, or SN74LVC1G29YEPR equivalent, key selection considerations include its NanoFree™ DSBGA (YZP) 8-ball package, 1.65–5.5 V wide-supply operation, Ioff-enabled back-drive protection, low ICC (10 µA max), and compatibility with mixed-voltage interface designs requiring level translation.
Technical Context
The SN74LVC1G29YEPR implements a positive-logic 2-of-3 decoding function where only one output goes low (Y0–Y2) based on A0/A1 states when G is low; all outputs go high when G is high. Its logic diagram confirms noninverting enable and inverting outputs - Y0, Y1, and Y2 are active-low, enabling direct connection to enable inputs of downstream devices without external inversion.
It integrates Ioff circuitry that disables outputs and blocks current flow when VCC = 0 V, supporting hot-plug and partial-power-down modes. Input tolerance up to 5.5 V allows interfacing with higher-voltage controllers while powered from lower VCC (e.g., 1.8 V or 2.5 V), and its design meets JESD 78 Class II latch-up immunity (>100 mA) and JESD 22 ESD ratings (2000-V HBM).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 1.65 V to 5.5 V - supports mixed-voltage system interfacing and battery-powered operation down to 1.65 V. |
| tpd (Max) | 5.1 ns at VCC = 3.3 V, CL = 15 pF - enables use in high-speed digital control paths with tight timing budgets. |
| Ioff Support | Yes - prevents damaging current backflow during power sequencing or hot-swap events, critical for modular systems. |
| Output Drive | ±24 mA at VCC = 3.3 V - sufficient to directly drive multiple LVC/LVT inputs or small LEDs without buffering. |
| Input Voltage Tolerance | Up to 5.5 V - allows 5-V logic signals to safely interface with 1.8-V or 2.5-V powered SN74LVC1G29YEPR. |
| ICC (Max) | 10 µA - ultra-low static power ideal for always-on subsystems and portable electronics. |
| Package | DSBGA (YZP), 8-ball, 1.5 mm × 1.5 mm, 0.5 mm height - smallest footprint among SN74LVC1G29 variants for ultra-dense PCB layouts. |
Pinout & Package
SN74LVC1G29YEPR uses the Texas Instruments NanoFree™ DSBGA (YZP) package - an 8-ball, 1.5 mm × 1.5 mm, 0.5 mm maximum height die-size ball grid array with bottom-side terminations. Pin 1 (GND) is located at corner A1 per JEDEC MO-220 standard layout.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| GND (Ball A1) | Ground reference | Primary return path for all internal logic and output currents; must be low-impedance connected to system ground plane. |
| Y2 (Ball A2) | Active-low decoded output | Asserts low when G = L and A1A0 = HH per function table; drives loads directly or enables downstream peripherals. |
| Y1 (Ball B1) | Active-low decoded output | Asserts low when G = L and A1A0 = HL; provides independent channel control without external inverters. |
| Y0 (Ball B2) | Active-low decoded output | Asserts low when G = L and A1A0 = LH; complements Y1/Y2 to form full 2-of-3 decode set. |
| A0 (Ball C1) | Address input bit 0 | LSB of 2-bit address bus; accepts voltages up to 5.5 V regardless of VCC level. |
| A1 (Ball C2) | Address input bit 1 | MSB of 2-bit address bus; sampled synchronously with G to determine active output. |
| G (Ball D1) | Enable input (active-low) | When low, enables decoding; when high, forces all Y outputs high - used for chip select or global disable. |
| VCC (Ball D2) | Power supply | Supplies core logic and output drivers; bypass capacitor (0.1 µF) required within 3 mm of this ball. |
Key Features
| Feature | Design Value |
|---|---|
| NanoFree™ DSBGA packaging | Eliminates traditional leadframe and mold compound - die itself serves as package, reducing size by >70% vs. SSOP and improving thermal resistance (θJA = 102°C/W). |
| Ioff partial-power-down protection | Automatically disables outputs and isolates I/O pins when VCC = 0 V, preventing back-driving and enabling safe live insertion in modular backplanes. |
| 5.5-V tolerant inputs | Allows direct connection to legacy 5-V microcontrollers or FPGAs without level shifters, simplifying mixed-voltage board design. |
| Low dynamic ground bounce (VOLP < 0.8 V) | Minimizes noise coupling into shared ground nets, critical for ADC reference stability and RF-sensitive sections in mixed-signal PCBs. |
| JESD 78 Class II latch-up immunity | Withstands >100 mA of injected current without destructive latch-up - ensures robustness in noisy industrial environments. |
Applications
| Memory Address Decoding | Peripheral Enable Selection |
|---|---|
Use Scenario: Selecting one of three SRAM or EEPROM chips on a microcontroller bus using two address lines and a chip-enable signal. IC Role / Device Role / Timing Role: SN74LVC1G29YEPR acts as a compact 2-to-3 address decoder, converting A0/A1 and CE into individual /CS signals for each memory device. Use Value: Replaces discrete logic or larger 74-series packages, saving >60% board area while maintaining sub-6 ns access timing margins. |
Use Scenario: Enabling one of three sensor interfaces (e.g., temperature, pressure, humidity) in a data acquisition module based on host command. IC Role / Device Role / Timing Role: SN74LVC1G29YEPR provides active-low enable outputs synchronized to host address and enable strobes. Use Value: Enables deterministic, glitch-free peripheral activation with no external pull-ups or timing delays required. |
| LED Segment Driver Control | Configurable Logic Signal Routing |
Use Scenario: Driving cathodes of three indicator LEDs in a status panel where only one LED illuminates at a time. IC Role / Device Role / Timing Role: SN74LVC1G29YEPR serves as a low-side switch controller, sinking current from LEDs tied to VCC via current-limiting resistors. Use Value: Delivers ±24 mA per output at 3.3 V - sufficient for bright visible-light LEDs without external transistors. |
Use Scenario: Routing clock or reset signals between processor cores and configurable peripherals in a multi-domain SoC test board. IC Role / Device Role / Timing Role: SN74LVC1G29YEPR functions as a programmable signal demultiplexer, selecting one of three destinations under software control. Use Value: Provides clean, rail-to-rail signal switching with <5.1 ns skew across outputs - essential for synchronous domain crossing. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar decoder/demultiplexer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC1G29DCUR | VSSOP-8 (DCU) package, 2.4 mm × 2.0 mm, 0.9 mm height - larger footprint but compatible with standard pick-and-place and reflow profiles. | Better suited for prototyping and low-volume assembly where DSBGA placement or inspection is impractical. | Select DCUR when board assembly lacks DSBGA capability or requires manual rework access. |
| SN74LVC1G29DCTR | SSOP-8 (DCT) package, 3.0 mm × 3.0 mm, 1.3 mm height - largest variant, with gull-wing leads for visual solder joint inspection. | Preferred for educational kits, serviceable modules, or legacy production lines not upgraded for fine-pitch BGA handling. | Choose DCTR for maximum manufacturability assurance and lowest risk in first-pass builds. |
Compared with SN74LVC1G29DCUR and SN74LVC1G29DCTR, the SN74LVC1G29YEPR delivers the smallest possible PCB footprint and lowest thermal resistance, making it optimal for miniaturized, thermally constrained designs - though it requires precision placement and X-ray inspection for reliability validation.
Availability
SN74LVC1G29YEPR is available at Aetrix Electronics and suitable for memory decoding, peripheral selection, LED control, and configurable signal routing requiring stable component supply across automotive infotainment, industrial HMIs, and portable medical devices.
Supply support for SN74LVC1G29YEPR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with over 50 years of innovation in high-reliability, low-power IC design.
The SN74LVC1G29YEPR belongs to TI's LVC logic family - engineered for wide-voltage operation, low power, and robust I/O integrity in space- and power-constrained digital systems.
FAQ
What is the function of the G input on the SN74LVC1G29YEPR?
The G input is an active-low enable control for the SN74LVC1G29YEPR. When G is low, the device performs 2-of-3 decoding on A0 and A1, driving exactly one of Y0–Y2 low. When G is high, all three outputs (Y0, Y1, Y2) are forced high, effectively disabling the decode function. This behavior is defined in the function table and confirmed in the logic diagram of the official SCES569C datasheet.
Does the SN74LVC1G29YEPR support level translation between different voltage domains?
Yes, the SN74LVC1G29YEPR supports level translation: its inputs tolerate up to 5.5 V regardless of VCC (1.65–5.5 V), allowing 5-V controllers to drive A0, A1, and G while the device operates from 1.8 V or 2.5 V. Outputs swing rail-to-rail (0 V to VCC), so Y0–Y2 are referenced to the local VCC - making it suitable for translating control signals into lower-voltage subsystems without external translators.
What package type does SN74LVC1G29YEPR use, and how does it differ from other variants?
SN74LVC1G29YEPR uses the NanoFree™ DSBGA (YZP) package - an 8-ball, 1.5 mm × 1.5 mm, 0.5 mm max height die-size BGA. Unlike the SSOP (DCT) and VSSOP (DCU) variants, YZP eliminates the leadframe and mold compound, placing solder balls directly on the silicon die. This reduces footprint by >70%, improves thermal performance (θJA = 102°C/W), and enables ultra-thin profile designs.
Can SN74LVC1G29YEPR be used in partial-power-down systems?
Yes, the SN74LVC1G29YEPR includes Ioff circuitry that disables outputs and blocks current flow when VCC = 0 V. This prevents back-driving and damaging current from flowing into the device during hot-swap or partial-power-down sequences - a feature verified in the Absolute Maximum Ratings and Electrical Characteristics tables of the SCES569C datasheet and compliant with JESD 78 Class II latch-up requirements.
What is the maximum output drive strength of SN74LVC1G29YEPR at 3.3 V?
At VCC = 3.3 V, the SN74LVC1G29YEPR delivers ±24 mA output drive - specifically, –24 mA for high-level output current (IOH) and +24 mA for low-level output current (IOL). This is specified in the Recommended Operating Conditions table and confirmed in the Electrical Characteristics section of the SCES569C datasheet, enabling direct drive of multiple LVC inputs or small indicator LEDs.
SN74LVC1G29YEPR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVC
- Package/Case:
- 8-VFSOP (0.091", 2.30mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Obsolete
- Type:
- Decoder/Demultiplexer
- Circuit:
- 1 x 2:3
- Independent Circuits:
- 1
- Current - Output High, Low:
- 32mA, 32mA
- Voltage Supply Source:
- Single Supply
- Voltage - Supply:
- 1.65V ~ 5.5V
- Operating Temperature:
- -40°C ~ 85°C
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 8-VSSOP
SN74LVC1G29YEPR FAQ
1.How can I place an order for SN74LVC1G29YEPR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LVC1G29YEPR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LVC1G29YEPR reliable?
The price and inventory of SN74LVC1G29YEPR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LVC1G29YEPR is usually 5 days.
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Once your SN74LVC1G29YEPR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LVC1G29YEPR?
For technical support, including SN74LVC1G29YEPR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LVC1G29YEPR requirements.
6.How does Aetrix verify that SN74LVC1G29YEPR is sourced from the original manufacturer or authorized distributors?
All SN74LVC1G29YEPR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LVC1G29YEPR meets industry standards.
7.What is the process for return or replacement of SN74LVC1G29YEPR?
All SN74LVC1G29YEPR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LVC1G29YEPR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LVC1G29YEPR part is unused and in its original packaging.
Return procedure for SN74LVC1G29YEPR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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