Texas Instruments SN74LVTH126DR
- Part No.:
- SN74LVTH126DR
- Manufacturer:
- Texas Instruments
- Package:
- 14-SOIC (0.154", 3.90mm Width)
- Datasheet:
-
SN74LVTH126DR.pdf
- Description:
- IC BUFFER NON-INVERT 3.6V 14SOIC
- Quantity:
- Payment:

- Shipping:

Inventory:177
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Product details
Overview
SN74LVTH126DR from Texas Instruments is a 3.3-V quad buffer with 3-state outputs and bus-hold inputs, designed for mixed-mode 5-V/3.3-V interfacing in industrial and telecom backplanes. It supports VCC down to 2.7 V, delivers 64 mA sink current per output, features Ioff and power-up 3-state for hot insertion, and operates from −40°C to 85°C.
For engineers reviewing the SN74LVTH126DR datasheet, SN74LVTH126DR pinout, SN74LVTH126DR application, or SN74LVTH126DR equivalent, this page provides verified electrical specs, SOIC-14 package details, bus-hold behavior, hot-swap capability, and direct alternatives for legacy 5-V system interfacing and low-voltage bus buffering.
Technical Context
The SN74LVTH126DR implements four independent noninverting buffers, each with an active-high output-enable (OE) control. Each output enters high-impedance state when its OE is low, enabling shared-bus operation without contention.
Its bus-hold circuitry actively maintains valid logic levels on undriven data inputs-eliminating external pullup/pulldown resistors-and its Ioff protection blocks current flow during power-down, satisfying JEDEC JESD78 Class II latch-up requirements (>100 mA).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.7 V to 3.6 V - Enables stable operation under unregulated battery supply or noisy rail conditions. |
| IOL / IOH | 64 mA / −32 mA - Sustains robust drive strength into heavy capacitive loads or TTL-compatible receivers. |
| tPLH / tPHL | 2.3 ns / 2.4 ns at VCC = 2.7 V - Ensures sub-5 ns propagation delay for timing-critical address/data paths. |
| Bus-Hold Current | ±75 µA at VCC = 3 V - Provides sufficient overdrive margin to reliably switch held inputs without external biasing. |
| Ioff Leakage | ±100 µA at VCC = 0 V - Prevents damaging backflow current during hot insertion or partial power-down sequences. |
| VOL / VOH | 0.5 V / 2.0 V at IOL = 64 mA / IOH = −32 mA - Guarantees TTL-compatible logic thresholds across full operating range. |
| ESD Rating | 2000-V HBM, 200-V MM, 1000-V CDM - Meets industrial-grade ESD immunity requirements without added protection circuitry. |
Pinout & Package
SN74LVTH126DR is housed in a 14-pin SOIC (D) package with 1.27 mm pitch, 8.75 mm × 3.91 mm body, and 1.75 mm max height. Pin 1 is marked by a beveled corner or notch.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | OE (Output Enable) | Active-high control per buffer; drives associated Y output to high-Z when low. |
| 2, 5, 9, 12 | A (Data Input) | Noninverting input with integrated bus-hold; retains last valid logic state when floating. |
| 3, 6, 11, 14 | Y (Output) | 3-state buffered output; sinks up to 64 mA or sources up to 32 mA in active state. |
| 7 | GND | Ground reference for all I/O and internal circuitry; must be connected before VCC during power sequencing. |
| 14 | VCC | 3.3-V supply input; supports operation down to 2.7 V; requires local 0.1 µF ceramic decoupling. |
Key Features
| Feature | Design Value |
|---|---|
| Mixed-mode interface | Accepts 5-V inputs while operating at 3.3-V VCC - enables seamless bridging between legacy 5-V logic and modern low-voltage systems. |
| Hot-insertion support | Ioff + power-up 3-state ensures zero current backflow and automatic high-Z on power ramp - eliminates bus conflicts during live card replacement. |
| Integrated bus-hold | Eliminates need for 10-kΩ external pullup/pulldown resistors on unused inputs - reduces BOM count and PCB area in high-density designs. |
| Low ground bounce | VOLP < 0.8 V at VCC = 3.3 V - minimizes noise coupling into adjacent signals during simultaneous switching events. |
| Latch-up immunity | Exceeds 100 mA per JESD 78 Class II - ensures robustness against transient-induced latch-up in harsh industrial environments. |
Applications
| Industrial Backplane Interface | Telecom Line Card Buffering |
|---|---|
Use Scenario: Interfacing 5-V microcontroller peripherals to 3.3-V FPGA-based control planes in programmable logic controllers. IC Role / Device Role / Timing Role: Level-shifting quad buffer providing direction-controlled data path isolation and bus contention prevention. Use Value: Eliminates discrete level translators and external biasing, reducing component count and signal integrity risk in multi-drop bus architectures. |
Use Scenario: Driving multiple 5-V transceiver enable lines from a 3.3-V baseband processor in modular line cards. IC Role / Device Role / Timing Role: Noninverting 3-state driver with fast enable/disable timing for synchronized peripheral activation. Use Value: Sub-5 ns propagation and enable delays ensure precise timing alignment across parallel transceiver channels. |
| Embedded Test Equipment I/O Expansion | Automated Test System (ATE) Signal Conditioning |
Use Scenario: Expanding GPIO count of a 3.3-V ARM-based test controller to drive legacy 5-V DUT interfaces. IC Role / Device Role / Timing Role: Bus-hold-equipped buffer maintaining valid states during reconfiguration or idle periods. Use Value: Prevents floating inputs from inducing false triggers or leakage paths during test sequence pauses or firmware updates. |
Use Scenario: Isolating and conditioning digital stimulus signals routed from 3.3-V pattern generators to 5-V DUT pins. IC Role / Device Role / Timing Role: High-drive-strength buffer with controlled rise/fall times and low ground bounce. Use Value: Delivers clean, jitter-free edges into capacitive ATE fixtures, minimizing timing uncertainty in high-speed functional tests. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC126A | No bus-hold; lower drive (24 mA sink); 1.65–3.6 V VCC range. | Requires external pullups for unused inputs; unsuitable for true hot-swap or floating-bus scenarios. | Select when cost sensitivity outweighs bus-hold necessity and system guarantees always-driven inputs. |
| SN74LVCH126A | Includes bus-hold and Ioff, but rated only to 3.6 V VCC (no 5-V tolerant inputs). | Cannot interface directly to 5-V sources; requires external clamping or level translation for mixed-voltage use. | Choose only in pure 3.3-V domains where 5-V compatibility is unnecessary and footprint compatibility is critical. |
Compared with SN74LVC126A and SN74LVCH126A, the SN74LVTH126DR uniquely combines 5-V input tolerance, bus-hold, Ioff, and 64-mA drive - making it the sole option for robust, no-resistor, hot-pluggable 5-V/3.3-V bus interfacing in industrial control and telecom infrastructure.
Availability
SN74LVTH126DR is available at Aetrix Electronics and suitable for industrial backplanes, telecom line cards, embedded test equipment, and automated test systems requiring stable component supply, long-term lifecycle assurance, and guaranteed traceability.
Supply support for SN74LVTH126DR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in logic interface solutions for industrial and communications markets.
The SN74LVTH126DR belongs to TI's LVTH logic family, engineered specifically for reliable mixed-voltage system interfacing, hot-swap readiness, and reduced board-level complexity in mission-critical infrastructure equipment.
FAQ
What voltage levels does SN74LVTH126DR accept on its inputs?
The SN74LVTH126DR accepts input voltages up to 5.5 V regardless of VCC, enabling direct connection to 5-V TTL or CMOS sources while operating at 3.3 V. This 5-V-tolerant input capability is explicitly specified in the absolute maximum ratings and electrical characteristics tables of the SCBS746B datasheet.
Does SN74LVTH126DR require external pullup or pulldown resistors on its inputs?
No. The SN74LVTH126DR integrates active bus-hold circuitry on all data inputs (A1–A4), which maintains the last valid logic state when inputs are floating. TI explicitly states that "use of pullup or pulldown resistors with the bus-hold circuitry is not recommended" - adding external resistors can degrade noise margin and increase power consumption.
Can SN74LVTH126DR be used in hot-insertion applications?
Yes. The SN74LVTH126DR includes both Ioff and power-up 3-state circuitry, which together disable outputs and force them into high-impedance during power-up, power-down, or partial power loss. This prevents damaging current backflow and bus contention - a key requirement validated per JEDEC JESD78 Class II latch-up testing.
What is the maximum output drive strength of SN74LVTH126DR?
The SN74LVTH126DR delivers up to 64 mA sink current (IOL) and −32 mA source current (IOH) per output at VCC = 3.3 V, as confirmed in the recommended operating conditions table. This exceeds standard LVTTL drive capability and supports driving heavier loads such as multiple 5-V inputs or unterminated transmission lines.
Is SN74LVTH126DR compatible with SOIC-14 footprints used for other TI logic devices?
Yes. SN74LVTH126DR uses the standard SOIC-14 (D) package with 1.27 mm lead pitch, 8.75 mm × 3.91 mm body dimensions, and JEDEC MS-012 variation AB outline. Its mechanical drawing (D0014A) matches TI's generic SOIC-14 footprint, ensuring drop-in compatibility with existing PCB layouts for SN74LVC126A, SN74LV126A, and similar devices.
SN74LVTH126DR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVTH
- Package/Case:
- 14-SOIC (0.154", 3.90mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 64mA
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-SOIC
SN74LVTH126DR FAQ
1.How can I place an order for SN74LVTH126DR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LVTH126DR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LVTH126DR reliable?
The price and inventory of SN74LVTH126DR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LVTH126DR is usually 5 days.
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Once your SN74LVTH126DR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LVTH126DR?
For technical support, including SN74LVTH126DR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LVTH126DR requirements.
6.How does Aetrix verify that SN74LVTH126DR is sourced from the original manufacturer or authorized distributors?
All SN74LVTH126DR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LVTH126DR meets industry standards.
7.What is the process for return or replacement of SN74LVTH126DR?
All SN74LVTH126DR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LVTH126DR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LVTH126DR part is unused and in its original packaging.
Return procedure for SN74LVTH126DR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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