Texas Instruments SN74LVTH126PWR
- Part No.:
- SN74LVTH126PWR
- Manufacturer:
- Texas Instruments
- Package:
- 14-TSSOP (0.173", 4.40mm Width)
- Datasheet:
-
SN74LVTH126PWR.pdf
- Description:
- IC BUF NON-INVERT 3.6V 14TSSOP
- Quantity:
- Payment:

- Shipping:

Inventory:1,243
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN74LVTH126PWR from Texas Instruments is a 3.3-V quad buffer with 3-state outputs and bus-hold circuitry, designed for mixed-mode interfacing between 3.3-V logic and 5-V TTL systems. It supports hot insertion via Ioff and power-up 3-state, operates down to 2.7 V, delivers ±64 mA output drive, and features <0.8 V output ground bounce at VCC = 3.3 V.
For engineers reviewing the SN74LVTH126PWR datasheet, SN74LVTH126PWR pinout, SN74LVTH126PWR application, or SN74LVTH126PWR equivalent, key selection criteria include its 14-pin TSSOP (PW) package, bus-hold input retention, 2.7–3.6 V supply range, and compatibility with legacy 5-V bus environments requiring level translation without external resistors.
Technical Context
The SN74LVTH126PWR implements four independent noninverting buffers, each with an active-high output-enable (OE) control. Its bus-hold circuitry actively maintains valid logic states on undriven inputs, eliminating need for external pullup/pulldown resistors - critical in high-density PCB layouts with floating traces.
Hot-insertion capability is enabled by dual protection mechanisms: Ioff disables outputs during power-down to prevent backflow current, while power-up 3-state ensures outputs remain high-impedance until VCC exceeds 1.5 V - both verified per JESD 78 Class II latch-up and JESD 22 ESD standards.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| VCC Range | 2.7 V to 3.6 V - enables stable operation across unregulated battery supplies and noisy industrial rails. |
| IOL / IOH | 64 mA / −32 mA - drives heavy capacitive loads or multiple TTL inputs without signal degradation. |
| tPLH/tPHL | 2.3 ns / 2.4 ns (VCC = 2.7 V) - supports >200 MHz data rates in short-bus applications. |
| Bus-Hold Current | ±75 µA at VCC = 3 V - reliably holds inputs at valid logic levels with minimal quiescent power penalty. |
| VIL/VIH | 0.8 V / 2.0 V - TTL-compatible input thresholds ensure robust recognition of 5-V signals at 3.3-V VCC. |
| VOHL/VOL | 2.0 V / 0.55 V (IOH = −32 mA, IOL = 64 mA) - meets TTL output voltage requirements for direct interface to legacy systems. |
Pinout & Package
TSSOP-14 (PW) package: 5.0 mm × 4.4 mm body, 0.65 mm lead pitch, 1.2 mm max height, exposed pad not present, RoHS-compliant NiPdAu lead finish, MSL Level-1.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| 1, 4, 10, 13 | Output Enable (OE) | Active-high control per buffer; ties to GND via pulldown if VCC < 1.5 V to guarantee Hi-Z state. |
| 2, 5, 11, 14 | Data Input (A) | Noninverting input with integrated bus-hold; no external termination required. |
| 3, 6, 12, 9 | Buffer Output (Y) | 3-state CMOS output capable of sourcing/sinking 64 mA/32 mA into TTL loads. |
| 7 | GND | Ground reference for all logic and output stages; must be low-impedance connection. |
| 14 | VCC | 3.3-V supply input; bypass capacitor (0.1 µF) required adjacent to pin for noise suppression. |
Key Features
| Feature | Design Value |
|---|---|
| Mixed-mode signal operation | Accepts 5-V inputs and drives 5-V TTL loads while powered from 3.3-V rail - eliminates discrete level shifters. |
| Bus-hold on all data inputs | Retains last valid logic state on floating inputs, reducing BOM count and layout complexity in unterminated buses. |
| Ioff and power-up 3-state | Prevents backflow current during hot-swap events and forces Hi-Z during power ramp - essential for modular backplane systems. |
| Latch-up immunity | Exceeds 100 mA per JESD 78 Class II - ensures reliability in electrically noisy industrial environments. |
| ESD protection | 2000-V HBM, 200-V MM, 1000-V CDM - reduces field failure risk during handling and assembly. |
Applications
| Industrial PLC Backplane Interface | Automotive Body Control Module Bus Extender |
|---|---|
Use Scenario: Interfacing 3.3-V microcontroller GPIOs to legacy 5-V CAN/LIN transceiver control lines in programmable logic controllers. IC Role / Device Role / Timing Role: Level-translating buffer with bus-hold, ensuring signal integrity during partial power-down of subsystems. Use Value: Eliminates need for four external pullup resistors and prevents undefined states during brownout conditions. | Use Scenario: Driving multiple 5-V sensor inputs (e.g., door lock actuators, window switches) from a 3.3-V automotive MCU in body electronics modules. IC Role / Device Role / Timing Role: Quad noninverting driver with hot-swap support, enabling safe module replacement without system shutdown. Use Value: Ioff protection prevents damage during live insertion; ±64 mA drive handles worst-case capacitive loading across harnesses. |
| Telecom Line Card Voltage Translation | Test Equipment Digital I/O Expander |
Use Scenario: Bridging 3.3-V FPGA I/O banks to 5-V legacy telecom switch fabric control buses in line cards. IC Role / Device Role / Timing Role: Low-skew buffer with sub-3 ns propagation delay, preserving timing margins in synchronous control paths. Use Value: 2.7–3.6 V operation accommodates aging power supplies; bus-hold avoids false triggers from crosstalk on long traces. | Use Scenario: Adding four additional 5-V-tolerant digital outputs to automated test equipment (ATE) controller boards using 3.3-V FPGAs. IC Role / Device Role / Timing Role: 3-state output expander with independent OE controls, allowing dynamic reconfiguration of test fixture signals. Use Value: Independent OE pins enable per-channel enable/disable without software overhead; 0.55 V VOL ensures solid TTL LOW recognition. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar quad 3-state buffer applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN74LVC126APW | No bus-hold; lower drive (±24 mA); 1.65–3.6 V VCC range. | Requires external pullups; unsuitable for floating-bus or hot-swap scenarios. | Select when cost sensitivity outweighs bus-hold and hot-swap needs. |
| SN74LVCH126APW | Includes bus-hold but lacks Ioff; same drive and voltage range. | Not rated for hot insertion; may suffer backflow current during partial power-down. | Choose for static board-level interfaces where hot-swap is not required. |
Compared with SN74LVC126APW and SN74LVCH126APW, the SN74LVTH126PWR uniquely combines bus-hold, Ioff, and 64 mA drive - making it the only option among the three qualified for live-replaceable modules interfacing to 5-V legacy infrastructure.
Availability
SN74LVTH126PWR is available at Aetrix Electronics and suitable for industrial automation, automotive body electronics, and telecom infrastructure requiring stable component supply with full production traceability and long-term lifecycle support.
Supply support for SN74LVTH126PWR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies with over 90 years of innovation in industrial, automotive, and communications markets.
The SN74LVTH126PWR belongs to TI's LVTH logic family, engineered specifically for robust 3.3-V-to-5-V mixed-signal interfacing in mission-critical systems where reliability under voltage transients and hot-swap conditions is mandatory.
FAQ
What is the maximum operating temperature range for the SN74LVTH126PWR?
The SN74LVTH126PWR is specified for operation from −40°C to +85°C ambient temperature. This industrial-grade range is validated per TI's recommended operating conditions and supported by thermal characterization data showing θJA = 113°C/W for the TSSOP-14 (PW) package, enabling reliable performance in enclosed enclosures without forced airflow.
Does the SN74LVTH126PWR require external pullup resistors on its inputs?
No, the SN74LVTH126PWR does not require external pullup or pulldown resistors because it integrates active bus-hold circuitry on all data inputs. This feature maintains the last valid logic state on undriven inputs, and TI explicitly advises against adding external resistors when bus-hold is enabled - doing so may cause contention or increased power consumption.
Can the SN74LVTH126PWR safely interface with 5-V inputs while powered at 3.3 V?
Yes, the SN74LVTH126PWR supports 5-V tolerant inputs at VCC = 3.3 V, with absolute maximum input voltage rated to 7 V and guaranteed VIH/VIL thresholds of 2.0 V/0.8 V - fully compatible with standard TTL logic levels. This mixed-mode capability is a core design feature confirmed in the device description and electrical characteristics tables.
What is the purpose of the Ioff specification in the SN74LVTH126PWR?
The Ioff specification in the SN74LVTH126PWR defines the maximum leakage current (±100 µA) that flows through outputs when VCC = 0 V and inputs/outputs are biased between 0–4.5 V. This parameter ensures safe hot insertion by preventing damaging backflow current into a powered-down device - a requirement verified for compliance with JESD 78 Class II latch-up standards.
Is the SN74LVTH126PWR pin-compatible with other packages in the LVTH126 family?
Yes, the SN74LVTH126PWR shares identical pinout and function mapping with all SN74LVTH126 variants including D (SOIC), DB (SSOP), NS (SOP), and DGVR (TVSOP) packages. Pin numbering, signal assignment (e.g., Pin 1 = 1OE, Pin 2 = 1A), and top-side marking conventions are consistent across all 14-pin configurations, enabling drop-in replacement based on board space and thermal requirements.
SN74LVTH126PWR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- 74LVTH
- Package/Case:
- 14-TSSOP (0.173", 4.40mm Width)
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Logic Type:
- Buffer, Non-Inverting
- Number of Elements:
- 4
- Number of Bits per Element:
- 1
- Input Type:
- -
- Output Type:
- 3-State
- Current - Output High, Low:
- 32mA, 64mA
- Voltage - Supply:
- 2.7V ~ 3.6V
- Operating Temperature:
- -40°C ~ 85°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
- 14-TSSOP
SN74LVTH126PWR FAQ
1.How can I place an order for SN74LVTH126PWR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN74LVTH126PWR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN74LVTH126PWR reliable?
The price and inventory of SN74LVTH126PWR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN74LVTH126PWR is usually 5 days.
3.What payment methods are accepted for SN74LVTH126PWR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN74LVTH126PWR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN74LVTH126PWR?
SN74LVTH126PWR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN74LVTH126PWR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN74LVTH126PWR?
For technical support, including SN74LVTH126PWR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN74LVTH126PWR requirements.
6.How does Aetrix verify that SN74LVTH126PWR is sourced from the original manufacturer or authorized distributors?
All SN74LVTH126PWR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN74LVTH126PWR meets industry standards.
7.What is the process for return or replacement of SN74LVTH126PWR?
All SN74LVTH126PWR units undergo pre-shipment inspection (PSI). If there is an issue with SN74LVTH126PWR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN74LVTH126PWR part is unused and in its original packaging.
Return procedure for SN74LVTH126PWR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN74LVTH126PWR Tags
-
SN74LVC1G17DBVR
Texas Instruments
-
SN74LVC1G07DCKR
Texas Instruments
-
SN74LVC1G17DCKR
Texas Instruments
-
SN74LVC1G07DBVR
Texas Instruments
-
SN74LVC1G125DCKR
Texas Instruments
-
SN74AHCT1G126DBVR
Texas Instruments
-
SN74LVC1G125DBVR
Texas Instruments
-
SN74AHCT1G125DBVR
Texas Instruments

-
SN74LVC2G17DBVR
Texas Instruments

-
SN74LVC2G07DCKR
Texas Instruments
-
SN74LVC1G34DCKR
Texas Instruments

-
SN74LVC2G17DCKR
Texas Instruments
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

