Texas Instruments SN74V3670-7PEU

Overview

SN74V3670 from Texas Instruments is a 8192 × 36-bit, 3.3-V CMOS synchronous FIFO memory with independent read/write clocks, user-selectable ×36/×18/×9 bus matching, and first-word fall-through (FWFT) or standard timing modes. It delivers 166-MHz operation (6-ns read/write cycle time), zero-latency retransmit capability, and programmable almost-empty/almost-full flags - deployed in high-throughput network packet buffering and video data stream alignment.

For engineers reviewing the SN74V3670 datasheet, SN74V3670 pinout, SN74V3670 application, or SN74V3670 equivalent, key selection considerations include its 128-pin TQFP package, 5-V-tolerant inputs, fixed low first-word latency, master/partial reset architecture, and dual-mode flag timing (synchronous/asynchronous) for real-time buffer monitoring.

Technical Context

This FIFO implements a dual-clock, depth-expandable architecture with independent WCLK and RCLK domains supporting fully asynchronous operation up to 166 MHz. Its RAM array is paired with configurable pointer logic, offset registers for PAE/PAF, and flag generation circuitry that supports both FWFT and standard timing modes selected at master reset via FWFT/SI.

Bus-matching is implemented through combinational control of BM, IW, and OW pins during master reset, enabling five input/output width configurations (e.g., ×36 in → ×9 out). Big-endian/little-endian byte ordering, interspersed/noninterspersed parity handling, and zero-latency retransmit (configured by RM) are all statically defined at initialization and retained across partial resets.

Key Specifications

Pinout & Package

SN74V3670 is housed in a 128-pin Thin Quad Flat Pack (TQFP) with 0.4-mm lead pitch, RoHS-compliant, and rated for 0°C to 70°C industrial operation.

Key Features

Applications

Equivalent & Alternatives

The following parts are listed as comparable options for similar FIFO memory applications.

Compared with IDT72V2115L15PF and NB3N502DR2G, SN74V3670 uniquely combines 8192 × 36-bit capacity with full ×36/×18/×9 bus matching, FWFT timing, and zero-latency retransmit - making it optimal for high-speed, adaptable data flow control where latency predictability and interface flexibility are critical.

Availability

SN74V3670 is available at Aetrix Electronics and suitable for network packet buffering, video frame synchronization, telecom line card interface, DSP data pipeline bridging, and high-speed protocol translation requiring stable component supply and long-term industrial availability.

Supply support for SN74V3670 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.

Manufacturer

Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and logic solutions, with decades of leadership in high-performance memory and interface ICs.

SN74V3670 belongs to TI's high-speed synchronous FIFO product line, engineered for deterministic data buffering in telecommunications infrastructure, broadcast video equipment, and real-time signal processing systems demanding sub-ns timing precision and flexible bus interfacing.

FAQ

What is the memory organization of the SN74V3670?

The SN74V3670 is organized as 8192 words × 36 bits, delivering 294,912 bits of total storage. This configuration is fixed for the SN74V3670 variant and distinct from other family members like SN74V3660 (4096 × 36) or SN74V3680 (16384 × 36). The memory is implemented in high-speed submicron CMOS and supports concurrent read/write operations via independent clock domains.

Does the SN74V3670 support 5-V logic inputs?

Yes, the SN74V3670 features 5-V-tolerant inputs on all control and data pins (D0–D35, WEN, REN, MRS, etc.), allowing direct connection to 5-V systems while operating from a 3.3-V supply. This eliminates the need for external level translators in mixed-voltage designs - a verified specification confirmed in the SCAS668A datasheet Absolute Maximum Ratings and DC Characteristics tables.

How does the first-word fall-through (FWFT) mode operate in the SN74V3670?

In FWFT mode, enabled by asserting FWFT/SI high during master reset, the first word written to an empty SN74V3670 appears on Q0–Q35 after exactly three rising edges of RCLK - without requiring REN to be asserted. Subsequent words still require REN activation. This behavior is hardware-implemented and deterministic, reducing pipeline startup latency in streaming applications.

Can the SN74V3670 be used in zero-latency retransmit mode?

Yes, the SN74V3670 supports zero-latency retransmit when the RM pin is held low during master reset. In this mode, asserting RT low on a rising RCLK edge causes the first retransmitted word to appear on the outputs synchronized to that same RCLK edge - verified in Figures 13–14 of the SCAS668A datasheet. This is distinct from normal-latency retransmit, which introduces one additional clock cycle delay.

What package type is used for the SN74V3670?

The SN74V3670 is packaged in a 128-pin Thin Quad Flat Pack (TQFP) with body size 14 mm × 14 mm and 0.4-mm lead pitch (PEU suffix). This RoHS-compliant package is specified for industrial temperature range (0°C to 70°C) and features exposed thermal pad construction per TI's packaging documentation for the SN74V36xx family.