Texas Instruments SN75DP126SSRHUR
- Part No.:
- SN75DP126SSRHUR
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 56-WFQFN Exposed Pad
- Datasheet:
-
SN75DP126SSRHUR.pdf
- Description:
- IC INTERFACE SPECIALIZED 56WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:782
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SN75DP126SSRHUR from Texas Instruments is a DisplayPort™ 1:2 re-driver switch with integrated TMDS translator, supporting one DP++ input routed to either a DP++ sink or an HDMI 1.4b/DVI-compatible TMDS sink. It delivers HBR2 signaling up to 5.4 Gbps on DP lanes and TMDS data rates up to 3.4 Gbps, features programmable input equalization (up to 18 dB), tunable DP output voltage swing (238–1300 mVpp) and pre-emphasis (0–9.5 dB), and operates across 0°C to 85°C in notebook and docking station video routing applications.
For engineers reviewing the SN75DP126SSRHUR datasheet, SN75DP126SSRHUR pinout, SN75DP126SSRHUR application, or SN75DP126SSRHUR equivalent, this page provides verified electrical specifications, I²C-configurable signal conditioning parameters, thermal performance data (RθJA = 35°C/W), fail-safe HPD/CAD interface behavior, and confirmed dual-supply (SN75DP126DS) / single-supply (SN75DP126SS) variant compatibility for system-level timing and power integrity validation.
Technical Context
The SN75DP126SSRHUR implements a dual-path re-driving architecture with independent equalization per DP input lane (configurable up to 18 dB for HBR2) and separate output conditioning for DP and TMDS paths. Its auto-configuration via DisplayPort link training dynamically adjusts input EQ and output VOD/pre-emphasis based on AUX channel feedback, enabling adaptive compensation for PCB trace loss and connector insertion loss.
It integrates dedicated DDC and AUX source/sink interfaces with built-in pull-up/pull-down resistors (60 kΩ SCL/SDA_SRC; 130 kΩ HPD inputs), supports priority-based sink selection via PRIORITY pin, and includes failsafe logic for HPD_SRC assertion during sink transitions. The device enters low-power Output Disable mode when no valid DP++ input signal is detected.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| DP Data Rate Support | HBR2 up to 5.4 Gbps - enables 4K@60Hz (YUV420) or QHD@144Hz over DisplayPort |
| TMDS Data Rate Support | Up to 3.4 Gbps - supports HDMI 1.4b resolutions >1920×1440 and 1080p deep color |
| Input Equalization Range | 0–18 dB (HBR2) - compensates up to ~20 dB channel loss at 2.7 GHz |
| Differential Output Swing (DP) | 238–1300 mVpp across four primary levels - configurable per lane for optimal eye opening |
| Pre-emphasis (DP) | 0–9.5 dB with secondary ±15% boost - fine-tunes high-frequency boost to counter inter-symbol interference |
| ESD Protection | ±2000 V HBM - meets IEC 61000-4-2 Level 2 for system-level robustness |
| Operating Temperature | 0°C to 85°C - qualified for commercial laptop, docking station, and embedded graphics applications |
Pinout & Package
SN75DP126SSRHUR is housed in a 56-pin WQFN package (11.00 mm × 5.00 mm) with exposed thermal pad. The package supports standard reflow profiles and requires decoupling capacitors on VCC (3.3 V) and VDD_DREG (1.05 V digital core supply).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN0p/IN0n – IN3p/IN3n | DP Main Link Lane 0–3 Differential Inputs | Accept RBR/HBR/HBR2 signals; support AC coupling with 75–200 nF caps and 100 Ω termination |
| DP_OUT0p/OUT0n – OUT3p/OUT3n | DP Main Link Lane 0–3 Differential Outputs | Programmable VOD (238–1300 mVpp) and pre-emphasis (0–9.5 dB); 50 Ω output impedance |
| TMDS_CLKp/n, TMDS_OUT0p/n – OUT2p/n | HDMI/DVI TMDS Clock & Data Lanes | Voltage-swing controlled by VSadj resistor (e.g., 4.7 kΩ → 1000 mVpp); slew rate set by SRC pin |
| AUX_SRCp/n, AUX_SNKp/n | Bidirectional DP AUX Channel Interfaces | Fail-safe operation with integrated 10 Ω on-resistance; support AUX link training and DPCD reads |
| SCL_SRC/SDA_SRC, SCL_SNK/SDA_SNK | DDC I²C Interfaces (Source & Sink) | 60 kΩ internal pull-ups on source side; 130 kΩ pull-downs on HPD inputs; support HDMI EDID reads |
| PRIORITY, HDMI_EN#, EN | Mode Selection & Power Control | PRIORITY selects DP vs HDMI sink priority; HDMI_EN# sets HDMI 1.4b or DVI 1.0 compliance; EN enables/disables all outputs |
Key Features
| Feature | Design Value |
|---|---|
| Auto-configuration via DP Link Training | Monitors AUX channel commands to dynamically adjust input EQ and output VOD/pre-emphasis without host MCU intervention |
| Glue-less GPU Interface | Direct compatibility with AMD, Intel, and NVIDIA graphics processors via native DDC/AUX separation and HPD/CAD signaling |
| Integrated DP-HDMI Adaptor ID Buffer | Accessible via DDC when HDMI/DVI sink is selected - reports HDMI capability to source for automatic protocol negotiation |
| Low-Power Operation Modes | Standby mode draws ~2 mW; Output Disable mode activates automatically on missing DP input signal |
| Tunable TMDS Output Slew Rate | Three-level SRC control (VIL/VIM/VIH) adjusts rise/fall times to meet HDMI tT1–tT3 timing specs across cable lengths |
Applications
| Notebook PC Video Routing | Desktop PC Docking Station |
|---|---|
Use Scenario: A laptop connects to external monitors via USB-C Alt Mode or mini-DP port requiring signal re-drive and protocol translation to HDMI or DP sinks. IC Role / Device Role / Timing Role: SN75DP126SSRHUR acts as a transparent re-driver and protocol-aware switch between DP++ source and dual-sink topology. Use Value: Enables reliable 4K@60Hz delivery over >10 cm PCB traces and passive cables while maintaining HDMI EDID handshake integrity. |
Use Scenario: A desktop docking station routes GPU output to multiple displays - one DP monitor and one HDMI TV - with dynamic sink selection. IC Role / Device Role / Timing Role: SN75DP126SSRHUR serves as a priority-controlled DP++ to DP/HDMI translator with automatic HPD arbitration. Use Value: Eliminates need for discrete level shifters and external DDC buffers; reduces BOM count by integrating AUX/DDC routing logic. |
| Standalone PC Video Card | Industrial Embedded Display Hub |
Use Scenario: A PCIe-based graphics card adds multi-monitor support using a single DP++ output to drive both DP and HDMI displays simultaneously. IC Role / Device Role / Timing Role: SN75DP126SSRHUR functions as a re-timer and sink selector, managing link training and signal integrity per active path. Use Value: Supports HBR2 data rates without requiring GPU-side re-timing; maintains backward compatibility with legacy DVI monitors. |
Use Scenario: An industrial HMIs uses a fixed-layout GPU to drive mixed-display environments (e.g., DP panel + HDMI signage) under extended temperature conditions. IC Role / Device Role / Timing Role: SN75DP126SSRHUR provides thermally stable signal conditioning (0°C–85°C) and failsafe HPD/CAD handling for unattended operation. Use Value: Ensures deterministic hot-plug detection and sink recognition even after repeated thermal cycling; avoids display enumeration failures. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar DisplayPort re-driver and TMDS translator applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TI SN75DP130RHUR | Single-input, dual-output DP++ re-driver with integrated HDMI 2.0 TMDS translator; supports 6 Gbps TMDS and FRL modes | Targets newer HDMI 2.0/2.1 systems requiring higher bandwidth; lacks DP-to-TMDS fallback mode of SN75DP126SSRHUR | Select SN75DP130RHUR for HDMI 2.0+ designs; retain SN75DP126SSRHUR for HDMI 1.4b/DVI legacy compatibility and lower power standby (~2 mW) |
| Parade Technologies PS8315-SP | DP++ to HDMI 1.4b re-driver with fixed 3.4 Gbps TMDS support; no DP sink output path; uses proprietary register map | Designed exclusively for HDMI sink routing; no DP-to-DP re-driving capability or PRIORITY-based dual-sink arbitration | Choose PS8315-SP only for HDMI-only applications where DP sink support is unnecessary and TI ecosystem integration is not required |
Compared with SN75DP130RHUR and PS8315-SP, SN75DP126SSRHUR uniquely supports bidirectional DP++ sink output *and* HDMI/DVI sink output from a single input, enabling flexible multi-protocol routing in space-constrained designs without sacrificing legacy DVI compatibility or ultra-low standby power.
Availability
SN75DP126SSRHUR is available at Aetrix Electronics and suitable for notebook PC video routing, desktop docking stations, and standalone PC video cards requiring stable component supply, long-term lifecycle assurance, and guaranteed traceable sourcing.
Supply support for SN75DP126SSRHUR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions, with decades of expertise in high-speed interface ICs and signal integrity engineering.
The SN75DP126SSRHUR belongs to TI's DisplayPort re-driver and protocol translator product line, designed specifically for mobile and desktop graphics subsystems needing seamless DP++ to HDMI/DVI interoperability with minimal layout overhead and zero firmware dependency.
FAQ
What is the maximum supported data rate for DP and HDMI modes on SN75DP126SSRHUR?
SN75DP126SSRHUR supports DisplayPort HBR2 signaling at 5.4 Gbps per lane (total 21.6 Gbps for 4 lanes) and HDMI 1.4b TMDS signaling up to 3.4 Gbps per data lane. These rates enable QHD@144Hz over DP and 1080p deep color over HDMI, validated per PHY_CTS test patterns and specified in the official TI datasheet revision SLLSEA9B.
Does SN75DP126SSRHUR require external configuration or can it operate autonomously?
SN75DP126SSRHUR operates autonomously using DisplayPort link training to auto-configure input equalization and output signal parameters. However, optional I²C configuration (via SCL_CTL/EQ and SDA_CTL/PRE pins) allows fine-tuning of VOD, pre-emphasis, and EQ settings. The SN75DP126SSRHUR also supports pin-strapping (e.g., PRIORITY, HDMI_EN#) for static mode selection without software.
How does SN75DP126SSRHUR handle hot-plug detection when both DP and HDMI sinks are connected?
SN75DP126SSRHUR uses the PRIORITY pin to resolve dual-sink contention: when low, DP sink takes precedence; when high, HDMI/DVI sink is selected. HPD_SRC asserts high for a fixed duration during sink transitions, ensuring reliable GPU detection. Both DP_HPD_SNK and TMDS_HPD_SNK inputs are 5-V tolerant with integrated 130 kΩ pull-downs for robust hot-plug signaling.
What power supply configurations does SN75DP126SSRHUR support?
SN75DP126SSRHUR (SS suffix) uses a single 3.3-V supply on VCC pins and a 1.05-V digital core supply on VDD_DREG. The dual-supply variant SN75DP126DS separates VDD (1.05 V) and VCC (3.3 V). All variants specify strict operating ranges: VCC = 3.0–3.6 V, VDD = 1.0–1.2 V, with shutdown current as low as 0.55 mA and standby current ~2 mW.
Is SN75DP126SSRHUR compatible with AMD, Intel, and NVIDIA GPUs out of the box?
Yes - SN75DP126SSRHUR is explicitly designed for glue-less interfacing with AMD, Intel, and NVIDIA graphics processors. It supports separate DDC and AUX channels, handles combined DDC/AUX sources, and includes integrated pull-up/pull-down resistors matching GPU reference schematics. TI confirms compatibility in the SLLSEA9B datasheet Section 1 and Application Report SZZA037.
SN75DP126SSRHUR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 56-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Desktop, Notebook PCs
- Interface:
- I2C
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 56-WQFN (5x11)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
SN75DP126SSRHUR FAQ
1.How can I place an order for SN75DP126SSRHUR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN75DP126SSRHUR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN75DP126SSRHUR reliable?
The price and inventory of SN75DP126SSRHUR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN75DP126SSRHUR is usually 5 days.
3.What payment methods are accepted for SN75DP126SSRHUR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN75DP126SSRHUR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN75DP126SSRHUR?
SN75DP126SSRHUR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN75DP126SSRHUR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN75DP126SSRHUR?
For technical support, including SN75DP126SSRHUR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN75DP126SSRHUR requirements.
6.How does Aetrix verify that SN75DP126SSRHUR is sourced from the original manufacturer or authorized distributors?
All SN75DP126SSRHUR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN75DP126SSRHUR meets industry standards.
7.What is the process for return or replacement of SN75DP126SSRHUR?
All SN75DP126SSRHUR units undergo pre-shipment inspection (PSI). If there is an issue with SN75DP126SSRHUR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN75DP126SSRHUR part is unused and in its original packaging.
Return procedure for SN75DP126SSRHUR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SN75DP126SSRHUR Tags

-
NVT4857UKAZ
NXP Semiconductors
-
TCA8418RTWR
Texas Instruments
-
PCA9546APWR
Texas Instruments

-
MD0100N8-G
Microchip Technology

-
PCA9548APW,118
NXP Semiconductors

-
PCA9540BDP,118
NXP Semiconductors

-
PCA9548APWR
Texas Instruments

-
PCA9546APW,118
NXP Semiconductors

-
PTN3360DBS,518
NXP Semiconductors

-
PCA9546ABS,118
NXP Semiconductors

-
PCA9518PWR
Texas Instruments

-
PCA9545APW,118
NXP Semiconductors
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

