Texas Instruments SN75DP129RHHR
- Part No.:
- SN75DP129RHHR
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 36-VFQFN Exposed Pad
- Datasheet:
-
SN75DP129RHHR.pdf
- Description:
- IC INTERFACE SPECIALIZED 36VQFN
- Quantity:
- Payment:

- Shipping:

Inventory:2,485
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Product details
Overview
SN75DP129RHHR from Texas Instruments is a DisplayPort-to-TMDS translator IC supporting dual-mode DP++ input and DVI/HDMI-compliant TMDS output at up to 2.5 Gbps, with integrated receiver equalization, active I²C buffer, HDMI/DVI connector recognition logic, and 12 kV ESD protection on all pins. It enables high-resolution video translation in dongles, docking stations, and discrete GPU add-in cards.
For engineers reviewing the SN75DP129RHHR datasheet, SN75DP129RHHR pinout, SN75DP129RHHR application, or SN75DP129RHHR equivalent, key selection criteria include its 36-pin QFN package, 0°C to 85°C operating range, TMDS voltage swing control via VSadj, HPD level-shifting capability with programmable VDD, and I²C_EN–enabled HDMI content compliance signaling.
Technical Context
The SN75DP129RHHR implements a full-featured physical-layer bridge between DisplayPort 1.1–compliant differential inputs (ML_IN 0–3, AUX_I2C) and TMDS outputs compliant with DVI 1.0 and HDMI 1.3 standards. Its internal architecture includes a receiver with adaptive equalization for lossy DP cables, a transmitter with fine-tunable TMDS output swing (via external VSadj resistor), and dual-path I²C functionality: one path (SCL/SDA) for sink-side DDC communication and another (AUX_I2C) for source-side auxiliary channel access.
It integrates dedicated logic for HDMI/DVI port identification using the I2C_EN pin, enabling conditional activation of an internal register that reports "DP-HDMI ADAPTOR" ASCII string over AUX_I2C-required for HDMI content authentication. The device supports low-power mode (LP pin) with <20 µW shutdown current and hot-plug detect (HPD_IN/HPD_OUT) with VDD-defined output voltage levels (1.8 V, 2.5 V, or 3.3 V).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data rate | Up to 2.5 Gbps - supports 1920×1200@60Hz or 1080p@60Hz with 12-bit color depth |
| Input interface | DisplayPort 1.1–compliant main link (4-channel differential) + AUX channel - accepts DP++ sources |
| Output interface | DVI 1.0 / HDMI 1.3–compliant TMDS (4-channel: CLK, 0, 1, 2) - fully interoperable with standard DVI/HDMI sinks |
| ESD rating | ±12 kV HBM on all pins - eliminates need for external TVS diodes in most board-level ESD designs |
| Supply rails | VCC = 3.0–3.6 V (TMDS core); VDD = 1.65–3.6 V (HPD level shifter); AVCC = 3.0–3.6 V (TMDS termination) |
| Operating temperature | 0°C to 85°C - qualified for commercial desktop, notebook, and docking station environments |
| Package | 36-pin 6×6 mm QFN (RHH) - exposes thermal pad for PCB heat dissipation; RoHS-compliant |
Pinout & Package
SN75DP129RHHR uses a 36-pin QFN package (RHH) with exposed thermal pad. Pin numbering follows top-view layout per TI SLAS583A; pin 1 is marked by dot or notch. Thermal pad must be soldered to PCB ground plane for reliable operation at full data rate.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| I2C_EN (32) | Control input | Enables HDMI connector identification logic; HIGH = HDMI mode (registers readable), LOW = DVI mode (registers disabled) |
| LP (33) | Control input | Low-power enable; HIGH = normal operation, LOW = high-impedance outputs & <20 µW quiescent draw |
| HPD_IN (15) / HPD_OUT (13) | Hot-plug detect I/O | HPD_IN monitors sink presence; HPD_OUT drives sink HPD line at VDD-defined logic level (1.8/2.5/3.3 V) |
| ML_IN x(p/n) (1–2, 4–5, 7–8, 34–35) | Differential input | Four DisplayPort main link lanes (Ch0–Ch3); support VID = 150–1400 mVpp differential input swing |
| TMDS_x(p/n) (20–21, 23–24, 26–27, 29–30) | Differential output | TMDS clock and data lanes (CLK, 0, 1, 2); VOD = 800–1200 mVpp into 50 Ω, tJITD ≤ 50 ps peak-to-peak |
| SCL (17) / SDA (16) | I²C bidirectional | Sink-side DDC interface; 100 kHz max; isolates source capacitance from cable/sink loading |
| AUX_I2C(p/n) (11–12) | I²C bidirectional | Source-side auxiliary channel; used to read HDMI/DVI identification register when I2C_EN = HIGH |
| VCC (3,9,18,22,28) / VDD (14) / AVCC (4) | Power supply | VCC powers TMDS transmitter; VDD sets HPD_OUT voltage; AVCC supplies TMDS termination network |
Key Features
| Feature | Design Value |
|---|---|
| Integrated TMDS level translator | Eliminates need for external level-shifting circuitry; ensures DVI/HDMI electrical compliance without redesign |
| Active I²C buffer | Isolates source-side I²C bus capacitance from cable and sink load, improving DDC signal integrity and margin for HDMI compliance testing |
| HDMI/DVI connector recognition | Hardware-based differentiation via I2C_EN pin enables legally compliant HDMI content handshaking without firmware intervention |
| Receiver equalization | Compensates for up to 15 dB channel loss at 1.25 GHz, extending usable DP cable length in dongle and dock applications |
| VSadj-controlled TMDS swing | External resistor adjusts TMDS output voltage swing (400–600 mV single-ended) to meet system-specific HDMI/DVI margin requirements |
Applications
| DisplayPort Dongle | Desktop PC GPU Add-in Card |
|---|---|
Use Scenario: Compact passive adapter converting DP++ output from laptop to HDMI monitor. IC Role / Device Role / Timing Role: Physical-layer protocol translator with embedded HPD management and HDMI content authentication signaling. Use Value: Enables plug-and-play HDMI connectivity while satisfying HDCP handshake requirements through I2C_EN–controlled register reporting. | Use Scenario: Discrete graphics card with native DP output adding HDMI port via on-board translation. IC Role / Device Role / Timing Role: High-speed TMDS transmitter with precise jitter control (tJITD ≤ 50 ps) and robust ESD protection (12 kV HBM). Use Value: Delivers stable 1080p/60Hz or 1920×1200 timing without external equalizers or level shifters, reducing BOM count and layout area. |
| Notebook Docking Station | Standalone Video Capture/Conversion Unit |
Use Scenario: Multi-port dock accepting DP input and routing video to HDMI display while maintaining USB/PCIe data paths. IC Role / Device Role / Timing Role: Signal integrity–optimized bridge with active I²C isolation to prevent DDC bus contention across multiple downstream ports. Use Value: Ensures reliable EDID reads and hot-plug detection across mixed-DVI/HDMI monitor configurations without host CPU involvement. | Use Scenario: Professional video equipment translating DP signals for HDMI recording or broadcast distribution. IC Role / Device Role / Timing Role: Low-jitter, high-fidelity TMDS driver meeting SMPTE/ITU-R BT.601 timing tolerances for broadcast-grade video. Use Value: Maintains sub-50 ps residual data jitter at 2.5 Gbps, preserving pixel accuracy and eliminating visible artifacts in critical monitoring applications. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar DisplayPort-to-TMDS translation applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| TI TPD12S016RGER | Single-chip solution integrating DP-to-TMDS translation + HDMI level shift + ESD protection + HPD buffer; no I²C_EN–based HDMI identification register | Targeted at cost-sensitive HDMI-only docks; lacks AUX_I2C–accessible identification string required for strict HDMI licensing | Select when HDMI content authentication is not required and board space is constrained |
| Parade Technologies PS8315B-VFQFN | Supports higher data rates (up to 5.4 Gbps), includes built-in spread-spectrum clocking, and offers configurable TMDS pre-emphasis; requires external VDD regulation | Designed for 4K-capable systems and industrial displays requiring extended cable reach and lower EMI | Select when future-proofing for UHD resolutions or stricter EMC requirements is needed |
Compared with SN75DP129RHHR, TPD12S016RGER reduces component count but sacrifices HDMI-compliance signaling capability, while PS8315B-VFQFN extends bandwidth and EMI performance at the cost of increased power and design complexity.
Availability
SN75DP129RHHR is available at Aetrix Electronics and suitable for DisplayPort dongles, desktop GPU add-in cards, notebook docking stations, and standalone video conversion units requiring stable component supply and long-term industrial availability.
Supply support for SN75DP129RHHR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity technologies, with decades of expertise in high-speed interface solutions.
The SN75DP129RHHR belongs to TI's DisplayPort physical layer product line, engineered specifically for seamless DP++ to DVI/HDMI translation in space-constrained, thermally demanding consumer and commercial video systems.
FAQ
What is the maximum data rate supported by the SN75DP129RHHR?
The SN75DP129RHHR supports a maximum data rate of 2.5 Gbps per lane, enabling transmission of 1080p60 video with 12-bit color depth or 1920×1200 resolution at 60 Hz. This rate aligns with DisplayPort 1.1 and HDMI 1.3 specifications, and the device maintains peak-to-peak residual data jitter below 50 ps at this speed under recommended operating conditions.
How does the SN75DP129RHHR handle HDMI versus DVI connector identification?
The SN75DP129RHHR uses the I2C_EN pin to control HDMI/DVI differentiation: when I2C_EN is HIGH, the internal I²C register becomes readable over AUX_I2C(p/n), returning the ASCII string "DP-HDMI ADAPTOR" to satisfy HDMI content authentication requirements; when LOW, the register is disabled, indicating DVI mode. This hardware-based method avoids firmware dependencies and ensures legal HDMI compliance.
What is the purpose of the VSadj pin on the SN75DP129RHHR?
The VSadj pin on the SN75DP129RHHR connects to an external resistor (typically 4.65 kΩ) to precisely adjust the TMDS output voltage swing between 400 mV and 600 mV single-ended. This allows system designers to tune output drive strength to meet specific HDMI or DVI compliance margins without modifying layout or adding external components.
Does the SN75DP129RHHR require separate power supplies for different functional blocks?
Yes, the SN75DP129RHHR uses three distinct supply domains: VCC (3.0–3.6 V) powers the TMDS transmitter core; VDD (1.65–3.6 V) sets the HPD_OUT logic-high voltage level; and AVCC (3.0–3.6 V) supplies the internal TMDS termination network. This separation enables flexible HPD voltage selection and optimized power delivery to each subsystem.
What ESD protection level does the SN75DP129RHHR provide, and how does it impact system design?
The SN75DP129RHHR provides ±12 kV HBM ESD protection on all pins, exceeding IEC 61000-4-2 Level 4 requirements. This eliminates the need for external TVS diodes on DP input, TMDS output, and I²C lines in most applications, simplifying PCB layout, reducing BOM cost, and improving signal integrity by avoiding parasitic capacitance from discrete protection devices.
SN75DP129RHHR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 36-VFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Desktop, Notebook PCs
- Interface:
- I2C, 2-Wire Serial
- Voltage - Supply:
- 1.65V ~ 3.6V
- Supplier Device Package:
- 36-VQFN (6x6)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
SN75DP129RHHR FAQ
1.How can I place an order for SN75DP129RHHR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN75DP129RHHR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN75DP129RHHR reliable?
The price and inventory of SN75DP129RHHR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN75DP129RHHR is usually 5 days.
3.What payment methods are accepted for SN75DP129RHHR?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SN75DP129RHHR transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SN75DP129RHHR?
SN75DP129RHHR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN75DP129RHHR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN75DP129RHHR?
For technical support, including SN75DP129RHHR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN75DP129RHHR requirements.
6.How does Aetrix verify that SN75DP129RHHR is sourced from the original manufacturer or authorized distributors?
All SN75DP129RHHR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN75DP129RHHR meets industry standards.
7.What is the process for return or replacement of SN75DP129RHHR?
All SN75DP129RHHR units undergo pre-shipment inspection (PSI). If there is an issue with SN75DP129RHHR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN75DP129RHHR part is unused and in its original packaging.
Return procedure for SN75DP129RHHR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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