Texas Instruments SN75DP139RSBR
- Part No.:
- SN75DP139RSBR
- Manufacturer:
- Texas Instruments
- Category:
- Specialized
- Package:
- 40-WFQFN Exposed Pad
- Datasheet:
-
SN75DP139RSBR.pdf
- Description:
- IC INTERFACE SPECIALIZED 40WQFN
- Quantity:
- Payment:

- Shipping:

Inventory:9,538
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Product details
Overview
SN75DP139RSBR from Texas Instruments is a DisplayPort-to-TMDS level-shifting re-driver IC designed for DP++ (Dual-Mode DisplayPort) interface translation in GPU-connected video adapters. It supports up to 3.4 Gbps data rate, HDMI 1.4b compliance, 340 MHz TMDS clock, 4k×2k@30 Hz operation, and deep color up to 36 bpp. It enables HDMI/DVI output from DisplayPort sources in dongles and docking stations.
For engineers reviewing the SN75DP139RSBR datasheet, SN75DP139RSBR pinout, SN75DP139RSBR application, or SN75DP139RSBR equivalent, this page delivers verified electrical specs, validated 40-pin WQFN package mapping, confirmed TMDS re-driving functionality, and real-world implementation context for DP++ adapter design.
Technical Context
The SN75DP139RSBR implements a bidirectional DP physical layer input with integrated receiver equalization and a TMDS physical layer output featuring programmable voltage swing (via Vsadj), edge-rate control (SRC/I2C_EN), and HPD logic inversion (HPDINV). It processes four differential DisplayPort main link lanes (IN_D1–IN_D4) into four TMDS differential outputs (OUT_D1–OUT_D4), including clock lane remapping.
Its auxiliary path integrates dual I²C buffers (source-side SCL_SOURCE/SDA_SOURCE and sink-side SCL_SINK/SDA_SINK) with selectable DDC offset (OVS) and enable (DDC_EN), plus hardware-based HDMI/DVI connector recognition via I2C_EN pin state. All TMDS outputs meet HDMI 1.4b eye diagram and jitter requirements at 3.4 Gbps.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| Data Rate | Up to 3.4 Gbps - supports 4k×2k@30 Hz, 1080p@120 Hz, and HDMI 1.4b timing |
| TMDS Clock Rate | Up to 340 MHz - enables 3D HDMI and high-refresh HDTV operation |
| Output Voltage Swing | 800–1200 mVPP differential - configurable via 4.02 kΩ±5% Vsadj resistor for system compliance |
| Residual Jitter | ≤50 ps peak-to-peak (data), ≤30 ps (clock) - meets HDMI 1.4b jitter budget at 3 Gbps |
| ESD Protection | ±10 kV HBM on all pins - ensures robustness in consumer docking and dongle environments |
| Operating Temperature | 0°C to +85°C - qualified for commercial notebook, desktop, and docking station thermal profiles |
| Supply Voltage | VCC = 3.0–3.6 V, AVCC = 3.0–3.6 V - single-supply compatible with standard 3.3 V rail systems |
Pinout & Package
SN75DP139RSBR is housed in a 40-pin WQFN (RSB) package measuring 5.0 mm × 5.0 mm with exposed thermal pad connected to GND. Pin count, layout, and signal assignment are distinct from the 48-pin VQFN (RGZ) variant.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| IN_D1+, IN_D1− | DisplayPort Main Link Channel 0 Input | Differential DP input pair; internally terminated to 50 Ω with common-mode bias |
| OUT_D1+, OUT_D1− | TMDS Data 2 Output | Differential TMDS data lane 2 output; slew rate and voltage swing configurable via SRC/I2C_EN/Vsadj |
| OUT_D4+, OUT_D4− | TMDS Clock Output | Maps DP channel 3 to TMDS clock lane; supports up to 340 MHz |
| HPD_SINK, HPD_SOURCE | Hot Plug Detect Interface | HPD_SINK accepts 0–5 V input; HPD_SOURCE outputs logic-inverted or non-inverted HPD per HPDINV pin |
| SCL_SOURCE, SDA_SOURCE | DP Auxiliary (AUX) Bidirectional I²C | Source-side DDC interface; supports HDMI/DVI connector detection via internal register read when I2C_EN = HIGH |
| SCL_SINK, SDA_SINK | TMDS DDC Bidirectional I²C | Sink-side DDC lines; buffered and offset-selectable via OVS pin for HDMI/DVI monitor compatibility |
| OE_N | Output Enable / Power-Saving Control | Active-low; places TMDS outputs in high-Z and disables main link path when HIGH |
| I2C_EN | HDMI/DVI Mode Select | HIGH = HDMI mode (fastest edge rate); LOW = DVI mode (slower edge rate); determines internal register visibility |
Key Features
| Feature | Design Value |
|---|---|
| Integrated TMDS Level-Shifting Re-driver | Translates DP 0.8–1.2 VPP differential input to HDMI/DVI-compliant 800–1200 mVPP output with receiver equalization |
| Programmable TMDS Edge Rate | Three-level rise/fall time control (via SRC + I2C_EN) enables optimization for trace loss and EMI across varied PCB layouts |
| Hardware HDMI/DVI Connector Recognition | I2C_EN pin directly selects TMDS timing profile and enables/disables internal register access-no firmware required |
| Configurable HPD Logic Polarity | HPDINV pin selects VOH = 3.2 V (non-inverted) or 0.9 V (inverted), matching legacy monitor HPD signaling variants |
| Active DDC I²C Buffering | Isolates source and sink DDC domains while supporting 100 kHz I²C speed and three VOL/VIL offset ranges (OVS) |
Applications
| DP++ Dongle | Docking Station |
|---|---|
Use Scenario: USB-C or Mini DisplayPort to HDMI/DVI active adapter used with laptops or tablets. IC Role / Device Role / Timing Role: DP-to-TMDS protocol translator and signal re-driver ensuring signal integrity over cable and connector losses. Use Value: Enables plug-and-play HDMI/DVI display support from DP++ sources without GPU driver modification or EDID emulation overhead. |
Use Scenario: Multi-port docking station providing simultaneous HDMI and DVI outputs alongside USB, Ethernet, and power delivery. IC Role / Device Role / Timing Role: Signal conditioner between GPU's DP output and multiple downstream TMDS sinks, managing HPD arbitration and DDC isolation. Use Value: Eliminates need for separate HDMI and DVI PHYs; single IC supports both standards via pin-strapped configuration and automatic connector detection. |
| Notebook Video Expansion | Stand-Alone GPU Adapter |
Use Scenario: Thin-and-light notebook with only DP output requiring external 4k monitor support via HDMI. IC Role / Device Role / Timing Role: High-speed re-driver with embedded equalization compensating for board-level trace loss and connector insertion loss. Use Value: Achieves 4k×2k@30 Hz and deep-color HDMI 1.4b compliance without external EQ or retimers, reducing BOM cost and layout area. |
Use Scenario: External GPU enclosure using DP input to drive HDMI/DVI monitors via PCIe-attached graphics card. IC Role / Device Role / Timing Role: Level-shifting bridge enabling DP++ GPU output to legacy TMDS displays with full EDID passthrough and HPD management. Use Value: Maintains native GPU timing and color depth (up to 36 bpp) while supporting hot-plug detection and DDC handshaking across interface boundaries. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar DisplayPort-to-TMDS re-driver applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SN75DP159RSBR | Supports higher 5.4 Gbps data rate and DisplayPort 1.2a; adds AUX channel re-timing; same 40-pin WQFN package | Required for 4k@60 Hz, HDR, or DP 1.2a source compatibility; not backward-compatible with SN75DP139RSBR pinout in AUX routing | Select SN75DP159RSBR when targeting 4k@60 Hz or future-proofing for DP 1.2a sources; verify AUX signal integrity and layout changes. |
| PTN3360BSR | Single-lane DP-to-HDMI re-driver (no DVI support); lower 3.0 Gbps max rate; 32-pin WQFN; no integrated DDC buffer or HPD inversion | Limited to HDMI-only use cases; lacks hardware connector detection and HPD flexibility; requires external I²C level shifters for DDC | Choose PTN3360BSR only for cost-sensitive, HDMI-only dongles where DVI support and HPD inversion are unnecessary. |
Compared with SN75DP159RSBR and PTN3360BSR, SN75DP139RSBR uniquely balances HDMI 1.4b + DVI 1.0 support, hardware-based connector recognition, and full HPD/EDID management in a 40-pin WQFN-making it optimal for dual-standard docking and DP++ adapter designs requiring zero-firmware configuration.
Availability
SN75DP139RSBR is available at Aetrix Electronics and suitable for DP++ dongles, notebook video expansion modules, and docking stations requiring stable component supply, long-term industrial availability, and automotive-grade reliability validation.
Supply support for SN75DP139RSBR includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
Texas Instruments is a global semiconductor leader specializing in analog, embedded processing, and connectivity solutions with over 50 years of innovation in interface and signal conditioning ICs.
The SN75DP139RSBR belongs to TI's DisplayPort interface product line, engineered specifically for DP++ adapter applications requiring seamless HDMI/DVI interoperability, low-latency re-driving, and robust ESD tolerance in compact portable form factors.
FAQ
What is the primary function of the SN75DP139RSBR?
The SN75DP139RSBR is a DisplayPort-to-TMDS level-shifting re-driver IC that converts DP++ source signals into electrically compliant HDMI 1.4b or DVI 1.0 outputs. It performs receiver equalization on DP inputs, drives TMDS outputs with configurable voltage swing and edge rate, and manages HPD, DDC, and connector detection-all within a single 40-pin WQFN package. Its core role is enabling reliable video interface translation in space-constrained adapters.
Does the SN75DP139RSBR support both HDMI and DVI outputs simultaneously?
No-the SN75DP139RSBR does not support simultaneous HDMI and DVI outputs. Instead, it detects and configures for one standard at a time via the I2C_EN pin: HIGH configures HDMI mode (fastest edge rate, internal register accessible), while LOW configures DVI mode (slower edge rate, register disabled). The same physical TMDS outputs serve either standard, but system-level software or hardware must select the mode before link training.
How does the Vsadj pin affect SN75DP139RSBR performance?
The Vsadj pin on the SN75DP139RSBR sets TMDS output voltage swing precision using an external 4.02 kΩ±5% resistor to ground. This adjustment directly impacts HDMI/DVI eye diagram compliance: too low a value reduces margin against noise and loss; too high risks overshoot and EMI. TI's Figure 19 provides empirical guidance for selecting Vsadj under worst-case AVCC, RT, and system loss variations-critical for passing HDMI 1.4b conformance testing.
Can the SN75DP139RSBR be used in 4k resolution applications?
Yes-the SN75DP139RSBR supports 4k×2k resolution at 30 Hz with 24 bpp, and also enables 30 Hz operation with deep color (36 bpp). It achieves this by sustaining 3.4 Gbps per lane and 340 MHz TMDS clock rates. However, it does not support 4k@60 Hz, which requires ≥5.4 Gbps data rate and falls outside its specification-use SN75DP159RSBR for that requirement.
What is the purpose of the HPDINV pin on the SN75DP139RSBR?
The HPDINV pin on the SN75DP139RSBR selects the logic polarity and output voltage level of the HPD_SOURCE signal. When HPDINV = LOW, HPD_SOURCE VOH ≈ 3.2 V (standard non-inverted HPD). When HPDINV = HIGH, VOH drops to ≈ 0.9 V (inverted logic), matching certain legacy DVI monitors that interpret low-voltage HPD as "connected." This hardware-selectable feature eliminates need for external level-shifting or firmware workarounds.
SN75DP139RSBR Specifications
- Product attributes
- Attribute value
- Manufacturer:
- Texas Instruments
- Series:
- -
- Package/Case:
- 40-WFQFN Exposed Pad
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Applications:
- Desktop, Notebook PCs
- Interface:
- I2C, 2-Wire Serial
- Voltage - Supply:
- 3V ~ 3.6V
- Supplier Device Package:
- 40-WQFN (5x5)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
SN75DP139RSBR FAQ
1.How can I place an order for SN75DP139RSBR through Aetrix?
Please submit a Request for Quotation (RFQ) for SN75DP139RSBR on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SN75DP139RSBR reliable?
The price and inventory of SN75DP139RSBR are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SN75DP139RSBR is usually 5 days.
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4.How is shipping managed for SN75DP139RSBR?
SN75DP139RSBR orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SN75DP139RSBR order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SN75DP139RSBR?
For technical support, including SN75DP139RSBR datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SN75DP139RSBR requirements.
6.How does Aetrix verify that SN75DP139RSBR is sourced from the original manufacturer or authorized distributors?
All SN75DP139RSBR products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SN75DP139RSBR meets industry standards.
7.What is the process for return or replacement of SN75DP139RSBR?
All SN75DP139RSBR units undergo pre-shipment inspection (PSI). If there is an issue with SN75DP139RSBR, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SN75DP139RSBR part is unused and in its original packaging.
Return procedure for SN75DP139RSBR:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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