NXP Semiconductors SPC5604BF2MLQ6
- Part No.:
- SPC5604BF2MLQ6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 144-LQFP
- Datasheet:
-
SPC5604BF2MLQ6.pdf
- Description:
- IC MCU 32BIT 512KB FLASH 144LQFP
- Quantity:
- Payment:

- Shipping:

Inventory:4,244
Please send an inquiry. Send us your inquiry, and we will respond immediately.
Product details
Overview
SPC5604BF2MLQ6 from NXP Semiconductors is a 32-bit automotive microcontroller based on the Power Architecture® e200z0h core, operating up to 64 MHz with 512 KB code flash, 64 KB data flash, and 48 KB SRAM - all featuring ECC protection. It integrates six FlexCAN modules, four LINFlex interfaces, three DSPI controllers, and a 10-bit ADC with 36 channels, targeting body control modules and gateway ECUs in 12 V automotive systems.
For engineers reviewing the SPC5604BF2MLQ6 datasheet, SPC5604BF2MLQ6 pinout, SPC5604BF2MLQ6 application, or SPC5604BF2MLQ6 equivalent, key selection criteria include its LQFP-144 package, FMPLL clock generation, Nexus 2+ debug interface, real-time counter with autonomous wakeup, and support for AUTOSAR-compliant timing via STM and PIT modules.
Technical Context
The SPC5604BF2MLQ6 implements the e200z0h CPU core with Variable Length Encoding (VLE) for reduced code footprint and operates at up to 64 MHz using its frequency-modulated PLL (FMPLL). Its crossbar switch enables concurrent access to flash, SRAM, and peripherals by multiple bus masters including eMIOS, FlexCAN, and DSPI.
It features a Memory Protection Unit (MPU) with eight region descriptors and 32-byte granularity, an Interrupt Controller (INTC) supporting 148 vectors, and a Boot Assist Module (BAM) enabling flash programming over CAN or SCI. The device includes dedicated hardware blocks for safety-critical functions: ECSM for error reporting, CTU for ADC-timer synchronization, and WKPU with 18 external wakeup sources.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | e200z0h 32-bit Power Architecture core with VLE instruction set for 30–40% smaller code size vs. standard encoding |
| Max Operating Frequency | 64 MHz - enables deterministic real-time response for automotive body control tasks |
| Flash Memory | 512 KB code flash + 64 KB data flash, both with ECC for ASIL-B compliance in safety-critical firmware storage |
| RAM | 48 KB SRAM with ECC - supports fault-tolerant runtime data handling in ECU applications |
| ADC | 10-bit, 36-channel analog-to-digital converter with CTU-triggered sampling for synchronized sensor acquisition |
| Communication Interfaces | 6 × FlexCAN (CAN 2.0B), 4 × LINFlex, 3 × DSPI, 1 × I²C - meets multi-bus vehicle network requirements |
| Timers & Counters | 56-channel eMIOS-lite, 6 × PIT, STM, RTC with 1 ms wakeup resolution - supports AUTOSAR OS timing and low-power sleep management |
| Debug & Test | Nexus 2+ interface per IEEE-ISTO 5001-2003 Class Two Plus, plus JTAG (IEEE 1149.1) for boundary scan and production test |
Pinout & Package
SPC5604BF2MLQ6 is housed in a 144-pin LQFP package (20 × 20 × 1.4 mm), RoHS-compliant and qualified for automotive temperature range (−40 °C to 125 °C). Pin assignments follow the MPC5604B/C family pinout specification for 144 LQFP, with dedicated supply domains (VDD_HV/VSS_HV, VDD_LV/VSS_LV, VDD_BV, VDD_HV_ADC/VSS_HV_ADC) and functional port multiplexing controlled via SIUL PCR registers.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| RESET | Asynchronous reset input | Pulled high after PHASE2 completion; initiates full system reset with noise filtering and Schmitt-trigger input |
| XTAL / EXTAL | Crystal oscillator inputs | Supports 4–16 MHz external crystal; tristated during reset to prevent unintended oscillation |
| VDD_HV / VSS_HV | Digital power/ground | Three pairs (pins 19, 51, 123 / 18, 47, 125) provide low-impedance digital supply path for core and peripherals |
| VDD_LV / VSS_LV | 1.2 V regulator decoupling | Three dedicated pairs require local 100 nF ceramic capacitors for stable internal voltage regulation |
| VDD_HV_ADC / VSS_HV_ADC | Analog reference supply/ground | Isolated analog domain pins (74/P14 and 73/R15) minimize digital switching noise coupling into ADC measurements |
| PA[0]–PA[15], PB[0]–PB[15], etc. | Configurable GPIO ports | 123 total I/O pins with programmable pad types (S/M/F), alternate functions (CAN, LIN, SPI, ADC), and WKPU interrupt capability |
Key Features
| Feature | Design Value |
|---|---|
| VLE-enabled e200z0h core | Reduces firmware memory footprint by ~35%, lowering flash cost and improving cache efficiency in resource-constrained ECUs |
| ECC-protected memories | Hardware detection and correction of single-bit errors in 512 KB flash, 64 KB data flash, and 48 KB SRAM - essential for ISO 26262 ASIL-B compliance |
| 6 × FlexCAN modules | Independent CAN controllers with configurable message buffers support multi-network gateways without external transceivers or arbitration logic |
| Crossbar switch architecture | Enables simultaneous DMA transfers (eDMA), CPU fetches, and peripheral accesses - eliminates bus contention in high-throughput body control applications |
| Real-time counter (RTC) | Autonomous 1 ms-resolution timer with 128 kHz or 16 MHz clock source, enabling wakeup from stop mode within 2 seconds without CPU intervention |
| Nexus 2+ debug interface | Provides real-time trace, non-intrusive breakpoints, and data watchpoints compliant with IEEE-ISTO 5001-2003 - accelerates AUTOSAR stack validation and calibration |
Applications
| Body Control Module (BCM) | Door Module ECU |
|---|---|
Use Scenario: Centralized control of lighting, window lifts, mirrors, locks, and interior sensors in modern passenger vehicles. IC Role / Device Role / Timing Role: Main application processor executing body control software, managing LIN-connected slave nodes, and coordinating CAN-based communication with gateway and instrument cluster. Use Value: 36-channel ADC enables direct connection of ambient light, rain, and position sensors; six FlexCAN modules allow seamless integration into multi-CAN domain architectures. |
Use Scenario: Intelligent door module handling power windows, central locking, anti-pinch detection, and mirror folding with local sensor feedback. IC Role / Device Role / Timing Role: Real-time controller running motor control algorithms (eMIOS PWM), sampling hall-effect and current-sense ADC inputs, and communicating status over LIN to BCM. Use Value: eMIOS-lite's 56 channels support simultaneous PWM generation, input capture for motor commutation, and pulse-width measurement for anti-pinch force estimation. |
| Roof Module Gateway | Seat Control Unit |
Use Scenario: Roof-mounted ECU aggregating sunroof, panoramic roof, and overhead console signals while bridging LIN and CAN networks. IC Role / Device Role / Timing Role: Protocol translator and message router between LINFlex-controlled switches/sensors and FlexCAN-connected body domain networks. Use Value: Four LINFlex modules handle up to 16 LIN slaves; dual CAN interfaces isolate roof domain traffic from chassis CAN, reducing bus load and improving diagnostics. |
Use Scenario: Motorized seat control unit managing lumbar, recliner, fore-aft, and heating functions with position feedback and thermal monitoring. IC Role / Device Role / Timing Role: Safety-aware controller performing position interpolation (ADC + eMIOS IC), heater PWM regulation, and fault logging to flash with ECC protection. Use Value: MPU enforces memory isolation between application, driver, and safety monitor partitions; RTC enables timed diagnostic self-tests during vehicle off-state. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SPC5604PF2MLQ6 | Same package and pinout; differs in flash configuration (384 KB code flash vs. 512 KB) and RAM (40 KB vs. 48 KB) | Suitable for less complex body ECUs with reduced firmware and data buffer requirements | Select when BOM cost optimization is prioritized and feature set fits design scope without requiring full 512 KB flash or 48 KB SRAM |
| MPC5604BF2MLQ6 | Identical silicon and electrical specs; differs only in branding (MPC prefix denotes legacy NXP part numbering vs. SPC prefix for STMicro/NXP joint branding) | No functional difference - used interchangeably in automotive OEM designs post-2015 | Verify manufacturer marking and date code; both share identical datasheet (MPC5604BC Rev. 15) and qualification data |
Compared with SPC5604BF2MLQ6, the SPC5604PF2MLQ6 offers lower memory resources for cost-sensitive entry-level modules, while the MPC5604BF2MLQ6 provides identical functionality under legacy naming - making the latter a drop-in alternative where procurement channels favor older part numbering conventions.
Availability
SPC5604BF2MLQ6 is available at Aetrix Electronics and suitable for automotive body electronics, gateway ECUs, and smart actuator control requiring stable component supply across extended product lifecycles and AEC-Q100 Grade 1 qualification.
Supply support for SPC5604BF2MLQ6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in functional safety and ASIL-certified microcontrollers.
The SPC5604BF2MLQ6 belongs to the SPC560x automotive MCU family, designed specifically for cost-optimized, safety-aware body electronics and gateway applications requiring robust CAN/LIN networking, ECC memory, and AUTOSAR-ready timing infrastructure.
FAQ
What is the maximum operating frequency of the SPC5604BF2MLQ6?
SPC5604BF2MLQ6 operates at a maximum frequency of 64 MHz, achieved via its integrated frequency-modulated phase-locked loop (FMPLL). This speed enables deterministic execution of AUTOSAR OS tasks and real-time control loops in body electronics applications while maintaining low power consumption through dynamic clock gating and power domain control.
Does the SPC5604BF2MLQ6 support AUTOSAR-compliant timing services?
Yes, SPC5604BF2MLQ6 supports AUTOSAR timing services through its System Timer Module (STM) and six Periodic Interrupt Timers (PIT), both offering 32-bit resolution and configurable prescalers. These modules generate precise, jitter-free interrupts required for OS scheduling, watchdog supervision, and time-triggered communication stacks in certified automotive software.
How many CAN interfaces does the SPC5604BF2MLQ6 integrate?
SPC5604BF2MLQ6 integrates six independent FlexCAN modules compliant with CAN 2.0B protocol. Each module supports configurable message buffers, flexible ID filtering, and automatic retransmission - enabling implementation of multi-domain gateways or distributed body networks without external CAN controllers or arbitration logic.
What debug interface does the SPC5604BF2MLQ6 provide?
SPC5604BF2MLQ6 provides a Nexus 2+ development interface compliant with IEEE-ISTO 5001-2003 Class Two Plus, supporting real-time trace, non-intrusive breakpoints, and data watchpoints. It also includes full JTAG (IEEE 1149.1) support for boundary scan testing and production programming, ensuring comprehensive development and test coverage.
Is the SPC5604BF2MLQ6 qualified for automotive temperature ranges?
Yes, SPC5604BF2MLQ6 is qualified per AEC-Q100 Grade 1, supporting operation from −40 °C to +125 °C ambient temperature. Its on-chip voltage regulator, thermal monitoring circuitry, and robust IO pad design ensure reliable performance in under-hood and cabin-mounted automotive ECU environments.
SPC5604BF2MLQ6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 144-LQFP
- Series:
- MPC56xx Qorivva
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z0h
- Core Size:
- 32-Bit Single-Core
- Speed:
- 64MHz
- Connectivity:
- CANbus, I2C, LINbus, SCI, SPI
- Peripherals:
- DMA, POR, PWM, WDT
- Number of I/O:
- 123
- Program Memory Size:
- 512KB (512K x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 32K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 36x10b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5604BF2MLQ6 FAQ
1.How can I place an order for SPC5604BF2MLQ6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5604BF2MLQ6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5604BF2MLQ6 reliable?
The price and inventory of SPC5604BF2MLQ6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5604BF2MLQ6 is usually 5 days.
3.What payment methods are accepted for SPC5604BF2MLQ6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5604BF2MLQ6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5604BF2MLQ6?
SPC5604BF2MLQ6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5604BF2MLQ6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5604BF2MLQ6?
For technical support, including SPC5604BF2MLQ6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5604BF2MLQ6 requirements.
6.How does Aetrix verify that SPC5604BF2MLQ6 is sourced from the original manufacturer or authorized distributors?
All SPC5604BF2MLQ6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5604BF2MLQ6 meets industry standards.
7.What is the process for return or replacement of SPC5604BF2MLQ6?
All SPC5604BF2MLQ6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5604BF2MLQ6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5604BF2MLQ6 part is unused and in its original packaging.
Return procedure for SPC5604BF2MLQ6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
SPC5604BF2MLQ6 Tags

-
ATTINY4-TSHR
Microchip Technology

-
ATTINY10-TSHR
Microchip Technology

-
ATTINY10-TS8R
Microchip Technology

-
ATTINY202-SSNR
Microchip Technology

-
ATTINY202-SSFR
Microchip Technology

-
ATTINY402-SSNR
Microchip Technology

-
PIC16F15213T-I/MF
Microchip Technology

-
PIC16F15213-E/MF
Microchip Technology

-
PIC10F200T-I/OT
Microchip Technology

-
ATTINY412-SSNR
Microchip Technology

-
PIC10F202T-I/OT
Microchip Technology

-
ATTINY404-SSNR
Microchip Technology
Tech Hub
A practical engineering guide to 3.3V and 5V logic compatibility, input thresholds, resistor dividers, translator ICs, MOSFET level shifting, I2C pull-ups, timing limits and power-sequencing risks.
The 74HC595 uses push-pull logic outputs, while the TPIC6B595 uses 50 V open-drain DMOS sinks for higher-power loads. This guide compares timing, current limits, 3.3 V interfacing, load wiring, thermal…
The 74HC595 converts serial data into eight stable parallel outputs. This guide covers pin functions, shift and storage timing, OE and MR behavior, drive-current limits, cascading, voltage compatibilit…
A technical comparison of level-sensitive latches and edge-triggered flip-flops, covering timing windows, setup and hold limits, master–slave operation, time borrowing, race-through, HDL inference and…
A D latch stores one bit while Enable controls when data can pass. This reference covers gate-level operation, truth tables, transparency, setup and hold timing, LE versus OE, common ICs and practical …
An SR latch stores one bit through cross-coupled feedback. This engineering reference covers NOR and NAND implementations, truth tables, forbidden-state recovery, gated operation, switch debouncing, fa…
Latch circuits retain one bit through feedback. This technical reference covers SR and D latches, truth tables, transparency, timing limits, latch-versus-flip-flop behavior, applications and common log…
An engineering guide to LED driver operation, constant-current and constant-voltage outputs, linear and switching topologies, dimming, IC selection, calculations, replacement compatibility, and fault c…
Operational amplifier guide covering op amp basics, feedback, ideal vs real op amps, common configurations, buffer circuits, offset, bias current, gain-bandwidth, slew rate, rail-to-rail limits and sel…
Jumper cables guide covering safe connection order, red and black clamp placement, final ground connection, cable gauge, length, clamp quality, copper vs CCA cables, jump starter comparison and battery…

