NXP Semiconductors SPC5673FK0MVY2R
- Part No.:
- SPC5673FK0MVY2R
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 516-BBGA
- Datasheet:
-
SPC5673FK0MVY2R.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 516FPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5673FK0MVY2R from NXP Semiconductors is a 32-bit Power Architecture® e200z7-based automotive microcontroller with dual-issue CPU, 3 MB on-chip flash, 192 KB SRAM (including 32 KB standby), 32-channel eMIOS, 64-channel eTPU2, and dual FlexCAN interfaces. It operates at 200 MHz nominal frequency, supports -40 °C to 125 °C ambient temperature, and targets engine control units and transmission control modules.
For engineers reviewing the SPC5673FK0MVY2R datasheet, SPC5673FK0MVY2R pinout, SPC5673FK0MVY2R application, or SPC5673FK0MVY2R equivalent, key selection criteria include its 516-ball TEPBGA package with EBI support, 200 MHz system clock capability, integrated eQADC with 64 analog channels, FlexRay controller, and Nexus debug interface compliant with IEEE-ISTO 5001-2003/2008.
Technical Context
The SPC5673FK0MVY2R implements a dual-issue e200z7 core with VLE instruction encoding for code density reduction and SPE2 extensions for DSP and single-precision floating-point operations. Its crossbar switch enables concurrent access to flash, SRAM, and peripherals by multiple bus masters including two eDMA2 controllers (64- and 32-channel).
It integrates two second-generation eTPU2 units sharing 24 KB code RAM and 6 KB parameter RAM, four eQADC modules supporting 64 analog inputs with decimation filters, and a frequency-modulated PLL (FMPLL) for precise clock generation. The device includes an external bus interface (EBI) - present only in 516-ball packages - for calibration and development use.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Core | e200z7 dual-issue 32-bit Power Architecture® core with VLE and SPE2 support |
| Flash Memory | 3 MB on-chip C90 flash with read-during-program/erase and EEPROM emulation capability |
| SRAM | 192 KB general-purpose SRAM, including 32 KB standby RAM for low-power retention |
| Operating Frequency | 200 MHz nominal system clock (fMAX = 200 MHz, no frequency modulation) |
| Temperature Range | -40 °C to +125 °C ambient operating range, qualified for automotive applications |
| Package | 516-ball TEPBGA (27 mm × 27 mm), Pb-free, with External Bus Interface (EBI) enabled |
| Analog Input Channels | 64-channel eQADC with eight decimation filters and one absolute reference channel |
Pinout & Package
SPC5673FK0MVY2R uses a 516-ball TEPBGA package (27 mm × 27 mm, Pb-free) with exposed thermal pad. Pin assignments follow the MPC5674F/MPC5673F family layout per Figure 11–15 of the Rev. 11 datasheet, supporting EBI signals (D_ADD[0–30], D_DAT[0–15], D_CS[0–3], D_OE, D_WE[0–3], D_ALE, D_RD_, D_TS, D_BDIP, CLKOUT) alongside dual FlexCAN, FlexRay, eSCI, DSPI, eMIOS, and eTPU2 I/O.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD / VSS | Core power supply / ground | Multiple dedicated VDD/VSS balls ensure stable 1.2 V core voltage regulation and noise immunity |
| VDDA_A0 / VDDA_B0 | Analog supply rails | Independent 3.3 V analog supplies for ADC A/B domains, enabling simultaneous high-resolution sampling |
| ANA[0–39] / ANB[0–23] | Analog input pins | 64 total analog inputs mapped across two eQADC modules; ANA/ANB groups support differential and single-ended modes |
| D_ADD[0–30] / D_DAT[0–15] | External Bus Interface address/data | Enables external memory expansion or calibration hardware interfacing during development and production test |
| CNRXA / CNRXB / CNTXA / CNTXB | FlexRay communication transceivers | Dual independent FlexRay channels with separate RX/TX pairs for time-triggered network redundancy |
| FR_A_TX / FR_A_RX / FR_B_TX / FR_B_RX | FlexRay signal routing | Direct connection to external FlexRay transceivers; supports protocol compliance up to 10 Mbps |
Key Features
| Feature | Design Value |
|---|---|
| Variable Length Encoding (VLE) | Reduces firmware footprint by up to 30% vs. pure 32-bit encoding, critical for flash-constrained automotive ECUs |
| eTPU2 with shared RAM | 64-channel timing unit with 24 KB code RAM and 6 KB parameter RAM enables complex real-time waveform generation without CPU load |
| FMPLL with frequency modulation | Supports spread-spectrum clocking to reduce EMI emissions in safety-critical vehicle subsystems |
| Boot Assist Module (BAM) | Enables serial bootload via CAN or SCI, simplifying field firmware updates and eliminating need for JTAG during production |
| Nexus Class III+ debug interface | IEEE-ISTO 5001-2003/2008 compliant trace and real-time debugging, essential for AUTOSAR and ISO 26262 toolchain integration |
Applications
| Engine Control Unit (ECU) | Transmission Control Module (TCM) |
|---|---|
|
Use Scenario: Real-time combustion timing, fuel injection pulse width, and knock detection in gasoline/diesel engines. IC Role / Device Role / Timing Role: Primary controller executing ASAM-MCD2 MC and AUTOSAR-compliant software with deterministic eTPU2-driven spark/fuel events. Use Value: 64-channel eQADC captures cylinder pressure and oxygen sensor data simultaneously; eTPU2 delivers sub-microsecond timing resolution for ignition control. |
Use Scenario: Clutch engagement scheduling, gear shift logic, and torque converter lock-up control in automatic transmissions. IC Role / Device Role / Timing Role: Safety-aware controller managing hydraulic solenoid actuation and CAN/FlexRay communication with powertrain domain controllers. Use Value: Dual FlexCAN interfaces enable redundant communication with engine and chassis ECUs; 192 KB SRAM supports multi-layer control algorithms with fault-tolerant state storage. |
| Electric Power Steering (EPS) | Brake Control Unit (BCU) |
|
Use Scenario: Motor current sensing, steering angle feedback processing, and assist torque calculation in column- or rack-mounted EPS systems. IC Role / Device Role / Timing Role: High-integrity motor controller interfacing with three-phase inverter gate drivers and torque sensors via eMIOS PWM and eQADC. Use Value: 32-channel eMIOS generates synchronized PWM outputs for motor phase control; eQADC decimation filters suppress switching noise in current sense measurements. |
Use Scenario: ABS/ESC hydraulic valve actuation, wheel speed monitoring, and brake-by-wire coordination in x-by-wire architectures. IC Role / Device Role / Timing Role: ASIL-D capable controller using dual-core lockstep not implemented, but leveraging ECC memory, ECSM error reporting, and FMPLL jitter control for functional safety. Use Value: On-chip ECSM monitors flash/SRAM integrity; FlexRay interface provides deterministic, time-triggered communication for brake command arbitration across distributed nodes. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| SPC5674FK0MVY3R | 4 MB flash, 256 KB SRAM, 264 MHz nominal clock, same 516-ball TEPBGA package with EBI | Higher memory and performance for next-gen ECU designs requiring larger AUTOSAR stacks or OTA update partitions | Select when >3 MB flash or >200 MHz timing margin is required; pin-compatible but requires revalidation of thermal and power delivery |
| SPC5673FK0MVR2R | 416-ball TEPBGA, no EBI, identical 200 MHz/3 MB/192 KB spec, Pb-free | Cost-optimized variant for space-constrained modules where external bus expansion is unnecessary | Choose for simplified PCB layout and lower BOM cost where EBI functionality is unused; requires package redesign due to different ball count and pitch |
Compared with SPC5673FK0MVY2R, SPC5674FK0MVY3R offers higher memory capacity and clock headroom for future-proofing, while SPC5673FK0MVR2R reduces package size and cost at the expense of EBI flexibility - both require full hardware and software requalification.
Availability
SPC5673FK0MVY2R is available at Aetrix Electronics and suitable for engine control units, transmission control modules, and electric power steering systems requiring stable component supply, long-term automotive lifecycle support, and AEC-Q100 qualification.
Supply support for SPC5673FK0MVY2R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in functional safety and ASIL-certified microcontrollers.
The SPC5673FK0MVY2R belongs to the SPC567xF family - designed specifically for high-performance, safety-critical automotive powertrain and chassis control applications requiring real-time determinism, robust diagnostics, and long-lifecycle support.
FAQ
What is the maximum operating frequency of the SPC5673FK0MVY2R?
The SPC5673FK0MVY2R has a nominal maximum operating frequency of 200 MHz with fMAX = 200 MHz. Unlike higher-speed variants such as SPC5674FK0MVY3R, it does not support frequency modulation; its FMPLL is configured for fixed-frequency operation. This specification is validated across the full -40 °C to +125 °C temperature range and aligns with AEC-Q100 Grade 1 requirements. The SPC5673FK0MVY2R achieves deterministic real-time performance without dynamic clock scaling.
Does the SPC5673FK0MVY2R include an external bus interface (EBI)?
Yes, the SPC5673FK0MVY2R includes an External Bus Interface (EBI), which is enabled exclusively in the 516-ball TEPBGA package configuration. Pins such as D_ADD[0–30], D_DAT[0–15], D_CS[0–3], D_OE, D_WE[0–3], and D_ALE are assigned per Figure 11–15 of the MPC5674F Rev. 11 datasheet. The EBI is intended for calibration equipment interfacing and application development - not for production runtime memory expansion - and is absent in 324- and 416-ball variants like SPC5673FK0MVV2R or SPC5673FK0MVR2R.
What analog-to-digital conversion capability does the SPC5673FK0MVY2R provide?
The SPC5673FK0MVY2R integrates four enhanced queued ADC (eQADC) modules supporting up to 64 analog input channels. It includes one absolute reference ADC channel and eight decimation filters to suppress high-frequency noise - particularly valuable for current sensing in motor control. Channel mapping spans ANA[0–39] and ANB[0–23] pins, with configurable sample-and-hold and queue-based conversion sequencing. This architecture enables simultaneous sampling across multiple sensors in engine or transmission control applications using the SPC5673FK0MVY2R.
Is the SPC5673FK0MVY2R pin-compatible with other MPC567xF family members?
The SPC5673FK0MVY2R is pin-compatible only with other 516-ball TEPBGA variants in the MPC567xF family, such as SPC5674FK0MVY3R and SPC5673FF3MVY2. It shares identical mechanical dimensions, ball pitch, and core peripheral pinouts (e.g., FlexCAN, FlexRay, eSCI, DSPI). However, it is not pin-compatible with 324- or 416-ball packages due to differing ball counts, signal muxing, and absence of EBI signals in smaller packages. Migration between SPC5673FK0MVY2R and SPC5674FK0MVY3R requires validation of thermal and power delivery but no PCB redesign.
What debug and trace capabilities does the SPC5673FK0MVY2R support?
The SPC5673FK0MVY2R features a Nexus Class III+ development interface compliant with IEEE-ISTO 5001-2003/2008, supporting real-time instruction trace, data trace, and non-intrusive breakpointing. It includes JTAG (IEEE 1149.1) for boundary scan and programming, plus Nexus-specific signals (NTRST, NCLK, NDATA[0–3], NTRG) routed to dedicated pins. These capabilities enable full AUTOSAR OS debugging, ISO 26262 verification, and toolchain integration with Lauterbach TRACE32 and iSYSTEM winIDEA - all directly supported on the SPC5673FK0MVY2R without external probes.
SPC5673FK0MVY2R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 516-BBGA
- Series:
- MPC56xx Qorivva
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z7
- Core Size:
- 32-Bit Single-Core
- Speed:
- 200MHz
- Connectivity:
- CANbus, EBI/EMI, SCI, SPI
- Peripherals:
- DMA, POR, PWM
- Number of I/O:
- 32
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 192K x 8
- Voltage - Supply (Vcc/Vdd):
- 1.08V ~ 5.25V
- Data Converters:
- A/D 64x12b
- Oscillator Type:
- External
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5673FK0MVY2R FAQ
1.How can I place an order for SPC5673FK0MVY2R through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5673FK0MVY2R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5673FK0MVY2R reliable?
The price and inventory of SPC5673FK0MVY2R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5673FK0MVY2R is usually 5 days.
3.What payment methods are accepted for SPC5673FK0MVY2R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5673FK0MVY2R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5673FK0MVY2R?
SPC5673FK0MVY2R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5673FK0MVY2R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5673FK0MVY2R?
For technical support, including SPC5673FK0MVY2R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5673FK0MVY2R requirements.
6.How does Aetrix verify that SPC5673FK0MVY2R is sourced from the original manufacturer or authorized distributors?
All SPC5673FK0MVY2R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5673FK0MVY2R meets industry standards.
7.What is the process for return or replacement of SPC5673FK0MVY2R?
All SPC5673FK0MVY2R units undergo pre-shipment inspection (PSI). If there is an issue with SPC5673FK0MVY2R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5673FK0MVY2R part is unused and in its original packaging.
Return procedure for SPC5673FK0MVY2R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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