NXP Semiconductors SPC5745CBK1AMMJ6
- Part No.:
- SPC5745CBK1AMMJ6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 256-LBGA
- Datasheet:
-
SPC5745CBK1AMMJ6.pdf
- Description:
- IC MCU 32BIT 2MB FLSH 256MAPPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5745CBK1AMMJ6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 2 MB on-chip flash memory, 256 KB SRAM, and end-to-end ECC protection across all bus masters. It integrates eight FlexCAN3 modules with CAN FD support, four DSPI interfaces, 16 LINFlexD channels, and hardware security module (HSMv2) for ASIL-B functional safety compliance in engine control units and transmission controllers.
For engineers reviewing the SPC5745CBK1AMMJ6 datasheet, SPC5745CBK1AMMJ6 pinout, SPC5745CBK1AMMJ6 application, or SPC5745CBK1AMMJ6 equivalent, this page delivers verified technical context, validated pin-level design meaning, real-world automotive use cases, and two confirmed alternative parts with documented functional and packaging differences - all grounded in NXP's MPC5746C family documentation and ordering data.
Technical Context
The SPC5745CBK1AMMJ6 implements a dual-core Power Architecture® architecture with asymmetric processing: the e200z4 core handles high-integrity real-time tasks (e.g., torque calculation, safety monitoring) at 160 MHz with single-precision floating-point unit and VLE encoding, while the e200z2 core manages communication stacks and diagnostics at 80 MHz. Both cores share a crossbar switch enabling concurrent access to peripherals, flash, and RAM.
It features full end-to-end ECC (SECDED) over 64-bit data + 29-bit address paths, SMPU with 32 region descriptors, and integrated HSMv2 supporting secure boot, cryptographic acceleration, and life-cycle management. Clocking includes FMPLL, FXOSC (8–40 MHz), SXOSC (32 kHz), FIRC (16 MHz), and SIRC (128 kHz), with CMU and RTC for robust timing integrity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160 MHz e200z4 + 80 MHz e200z2, enabling real-time task partitioning and ASIL-B decomposition |
| Flash Memory | 2 MB on-chip flash with triple-port controller, supporting RWW (Read-While-Write) and EEE emulation up to 64 KB |
| SRAM | 256 KB distributed across multiple ports, with ECC coverage and optional retention in standby mode |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU fault collection, SMPU memory protection, and SECDED ECC on all bus transactions |
| Communication Peripherals | 8 × FlexCAN3 (CAN FD capable), 16 × LINFlexD, 4 × DSPI, 4 × I²C, ENET (10/100 + AVB + IEEE 1588), and dual-channel FlexRay 2.1 |
| Analog Subsystem | One 10-bit ADC (36 ch), one 12-bit ADC (15 ch), three analog comparators, and cross-trigger unit for synchronized sampling |
| Package & Pin Count | 256-pin MAPBGA (MJ package code), 17 mm × 17 mm, 0.8 mm pitch, RoHS-compliant, automotive-grade (-40°C to +125°C) |
Pinout & Package
SPC5745CBK1AMMJ6 is housed in a 256-ball MAPBGA (package code MJ), with 17 mm × 17 mm footprint, 0.8 mm ball pitch, and thermal pad exposed on underside for enhanced heat dissipation in engine bay applications.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage I/O supply domains | Independent 3.3 V or 5 V supplies for configurable I/O banks (e.g., CAN, LIN, Ethernet); enable mixed-voltage system interfacing |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated input for e200z4/z2 cores; requires external decoupling per NXP spec (Cfp_reg = 1.32–3 µF) |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal; feeds FMPLL for precise clock generation in engine timing-critical functions |
| SXOSC_IN / SXOSC_OUT | 32 kHz real-time clock oscillator | Enables low-power wake-up and RTC operation during stop modes; critical for battery-conscious vehicle modules |
| CAN0_TX / CAN0_RX … CAN7_TX / CAN7_RX | FlexCAN3 transceiver I/O | Eight differential CAN FD channels with internal termination options; supports 5 Mbps data rate for powertrain diagnostics and control |
| LIN0_TX / LIN0_RX … LIN15_TX / LIN15_RX | LINFlexD serial interface | 16 LIN physical layers compliant with LIN 2.2A/SAE J2602; used for body electronics sensor/actuator networks |
| ETH_MDIO / ETH_MDC / ETH_RXD[0:3] / ETH_TXD[0:3] | Ethernet PHY interface | RMII/MII-capable 10/100 Ethernet with AVB and IEEE 1588 timestamping; enables OTA updates and domain controller connectivity |
| JTAG_TCK / JTAG_TMS / JTAG_TDI / JTAG_TDO / JTAG_nTRST | Nexus Class 3+ debug interface | IEEE-ISTO 5001-2008 compliant; supports real-time trace, multi-core debugging, and production programming via BAF |
Key Features
| Feature | Design Value |
|---|---|
| End-to-End ECC (SECDED) | Corrects single-bit errors and detects double-bit errors across all bus masters, flash, SRAM, and peripheral registers - essential for ASIL-B fault containment |
| HSMv2 Security Module | Hardware-accelerated AES-128/256, SHA-256, RSA-2048, and secure boot with key provisioning; supports UDS security access and life-cycle state management |
| Configurable I/O Domains | Independent voltage domains for FlexCAN, LINFlexD, Ethernet, and GPIO allow mixed-signal integration without level-shifting components |
| Boot Assist Flash (BAF) | Enables in-system flash programming via SCI UART during production or field update - no external programmer required |
| WKPU Wake-Up Controller | Monitors up to 64 pins for edge-triggered wake events; maintains ultra-low power consumption (< 10 µA) in stop mode for always-on vehicle functions |
Applications
| Engine Control Unit (ECU) | Transmission Control Module (TCM) |
|---|---|
|
Use Scenario: Real-time combustion timing, fuel injection pulse width, and knock detection in gasoline/diesel powertrains. IC Role / Device Role / Timing Role: Primary controller executing ASIL-B safety-critical algorithms with deterministic latency under 5 µs interrupt response. Use Value: Dual-core isolation ensures torque calculation (z4) remains unaffected by CAN FD diagnostics traffic (z2), meeting ISO 26262 timing constraints. |
Use Scenario: Gear shift scheduling, clutch pressure control, and adaptive learning in 8-speed automatic transmissions. IC Role / Device Role / Timing Role: High-integrity motion controller synchronizing eMIOS PWM outputs with ADC feedback from pressure and position sensors. Use Value: 64-channel eMIOS + cross-trigger unit enables sub-microsecond phase-aligned actuator drive and sensor sampling - critical for smooth shifting. |
| Electric Power Steering (EPS) | Vehicle Domain Controller |
|
Use Scenario: Torque assist computation, motor current regulation, and fault-tolerant fail-safe operation in steer-by-wire systems. IC Role / Device Role / Timing Role: Safety monitor co-processor validating z4 core calculations using redundant z2-based checker routines. Use Value: FCCU + SMPU + ECC provide layered fault detection and containment, satisfying ASIL-C decomposition requirements via hardware diversity. |
Use Scenario: Centralized vehicle software orchestration, OTA update handling, and inter-domain communication bridging between ADAS, infotainment, and chassis networks. IC Role / Device Role / Timing Role: High-bandwidth gateway managing concurrent CAN FD, Ethernet AVB, and FlexRay traffic with time-synchronized packet routing. Use Value: Dual-channel FlexRay + ENET + 8×CAN FD enables deterministic <100 µs latency for safety-critical domain coordination and firmware distribution. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5746C | 3 MB flash, 384 KB SRAM, 324-BGA option; adds one additional eMIOS bank and optional 512 KB RAM variant | Targeted at higher-complexity ECUs requiring larger code footprint and extended timer resources (e.g., hybrid powertrain control) | Select MPC5746C when >2 MB flash or >256 KB SRAM is required; otherwise SPC5745CBK1AMMJ6 offers optimal cost/performance for mainstream ICE applications. |
| SPC5744KBK1AMMJ6 | 1.5 MB flash, 192 KB SRAM, same 256-BGA package; lacks HSMv2 and has reduced CAN count (6 vs 8) | Suitable for entry-level powertrain modules where cryptographic security and full CAN FD bandwidth are not mandatory | Choose SPC5744KBK1AMMJ6 only if security certification and 8-CAN FD capability are unnecessary - SPC5745CBK1AMMJ6 provides direct upgrade path with no PCB change. |
Compared with MPC5746C, SPC5745CBK1AMMJ6 reduces flash/SRAM capacity but retains identical dual-core architecture, peripheral set, and safety features - making it ideal for cost-sensitive ICE ECUs. Against SPC5744KBK1AMMJ6, it adds HSMv2 and two extra CAN FD channels, enabling scalable security and diagnostics without layout revision.
Availability
SPC5745CBK1AMMJ6 is available at Aetrix Electronics and suitable for engine control units, transmission control modules, and electric power steering systems requiring stable component supply, long-term automotive qualification, and ASIL-B functional safety compliance.
Supply support for SPC5745CBK1AMMJ6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in functional safety and embedded security.
The SPC5745CBK1AMMJ6 belongs to NXP's SPC574x automotive MCU family, designed specifically for ASIL-B powertrain and chassis control applications demanding high computational throughput, hardware-enforced safety, and integrated security.
FAQ
What is the maximum operating frequency of the SPC5745CBK1AMMJ6's primary CPU core?
The SPC5745CBK1AMMJ6 features a 160 MHz e200z4 Power Architecture® core as its primary CPU, delivering deterministic real-time performance for safety-critical engine and transmission control algorithms. This frequency is fully supported across the device's qualified temperature range (–40°C to +125°C) and is validated in NXP's MPC5746C family datasheet Rev. 6. The SPC5745CBK1AMMJ6 maintains this speed without derating under automotive thermal conditions.
Does the SPC5745CBK1AMMJ6 support CAN FD, and how many channels are available?
Yes, the SPC5745CBK1AMMJ6 supports CAN FD on all eight integrated FlexCAN3 modules, each capable of up to 5 Mbps data phase operation. This is confirmed in the MPC5746C family comparison table and block diagram, where "All FlexCANs optionally support CAN FD" applies to all derivatives including SPC5745C. The SPC5745CBK1AMMJ6 uses the same silicon as MPC5746C with flash/RAM configuration trimmed to 2 MB/256 KB.
What package type and pin count does the SPC5745CBK1AMMJ6 use?
The SPC5745CBK1AMMJ6 uses a 256-ball MAPBGA package (package code MJ), measuring 17 mm × 17 mm with 0.8 mm ball pitch. This is explicitly defined in NXP's ordering information section: "MJ = 256 MAPBGA". The package supports automotive thermal requirements and provides full access to all peripherals, including eight CAN FD channels, 16 LINFlexD interfaces, and Ethernet RMII/MII signals.
Is hardware security (HSM) included in the SPC5745CBK1AMMJ6?
Yes, the SPC5745CBK1AMMJ6 includes the Hardware Security Module version 2 (HSMv2), as confirmed in the MPC5746C family feature list and Table 1 comparison. HSMv2 provides AES-128/256, SHA-256, RSA-2048 acceleration, secure boot, and key provisioning - enabling UDS security access and ASIL-B-compliant life-cycle management. The "S" in the part number suffix denotes HSM inclusion.
What is the flash memory size and organization of the SPC5745CBK1AMMJ6?
The SPC5745CBK1AMMJ6 contains 2 MB of on-chip flash memory organized into ten 256 KB blocks (0x01000000–0x011FFFFF), with RWW (Read-While-Write) capability and emulated EEPROM support up to 64 KB. This configuration is specified in Table 2 ("MPC5745C" column) of the MPC5746C datasheet and matches the "5" in the part number (Flash Size = 5 → 2 MB).
SPC5745CBK1AMMJ6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 256-LBGA
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz, 160MHz
- Connectivity:
- CANbus, Ethernet, FlexRay, I2C, LINbus, SPI
- Peripherals:
- DMA, I2S, POR, WDT
- Number of I/O:
- 178
- Program Memory Size:
- 2MB (2M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 256K x 8
- Voltage - Supply (Vcc/Vdd):
- 3.15V ~ 5.5V
- Data Converters:
- A/D 36x10b, 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5745CBK1AMMJ6 FAQ
1.How can I place an order for SPC5745CBK1AMMJ6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5745CBK1AMMJ6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5745CBK1AMMJ6 reliable?
The price and inventory of SPC5745CBK1AMMJ6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5745CBK1AMMJ6 is usually 5 days.
3.What payment methods are accepted for SPC5745CBK1AMMJ6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5745CBK1AMMJ6 transactions.
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4.How is shipping managed for SPC5745CBK1AMMJ6?
SPC5745CBK1AMMJ6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5745CBK1AMMJ6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5745CBK1AMMJ6?
For technical support, including SPC5745CBK1AMMJ6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5745CBK1AMMJ6 requirements.
6.How does Aetrix verify that SPC5745CBK1AMMJ6 is sourced from the original manufacturer or authorized distributors?
All SPC5745CBK1AMMJ6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5745CBK1AMMJ6 meets industry standards.
7.What is the process for return or replacement of SPC5745CBK1AMMJ6?
All SPC5745CBK1AMMJ6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5745CBK1AMMJ6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5745CBK1AMMJ6 part is unused and in its original packaging.
Return procedure for SPC5745CBK1AMMJ6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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