NXP Semiconductors SPC5746BBK1AMKU2
- Part No.:
- SPC5746BBK1AMKU2
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5746BBK1AMKU2.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5746BBK1AMKU2 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash memory, 384 KB SRAM with end-to-end ECC, and ISO 26262 ASIL-B functional safety certification. It integrates eight FlexCAN3 modules with CAN FD support, dual-channel FlexRay, 10/100 Ethernet with AVB and IEEE 1588, and hardware security module (HSMv2). It is designed for engine control units (ECUs), transmission control, and chassis domain controllers.
For engineers reviewing the SPC5746BBK1AMKU2 datasheet, SPC5746BBK1AMKU2 pinout, SPC5746BBK1AMKU2 application, or SPC5746BBK1AMKU2 equivalent, key selection criteria include dual-core deterministic real-time performance, ASIL-B compliance, integrated CAN FD/FlexRay/Ethernet connectivity, HSMv2-based secure boot, and 176-pin LQFP-EP packaging for automotive ECU layout compatibility.
Technical Context
The SPC5746BBK1AMKU2 implements a tightly coupled dual-core architecture where the e200z4 core handles high-intensity control tasks (e.g., combustion timing, torque calculation) and the e200z2 core manages communication stacks and diagnostics. Both cores operate with variable-length encoding (VLE) and share access to memory via a crossbar switch with SMPU-enforced region protection.
Its clock system includes FMPLL with frequency modulation, multiple oscillators (FXOSC 8–40 MHz, SXOSC 32 kHz, FIRC 16 MHz, SIRC 128 kHz), and Clock Monitor Unit (CMU) for fail-safe monitoring. All bus masters generate SECDED codes covering 64-bit data + 29-bit address, ensuring full ECC coverage across flash, SRAM, and peripheral interfaces.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160 MHz e200z4 + 80 MHz e200z2, both with VLE and single-precision floating-point unit (SPFP-APU) |
| Flash Memory | 3 MB on-chip flash with triple-port controller, 3-page buffers, and EEPROM emulation up to 128 KB |
| SRAM | 384 KB distributed across 8 RAM ports, all protected by end-to-end ECC (SECDED) |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU fault collector, SMPU with 32 regions, and memory BIST |
| Communication Interfaces | 8 × FlexCAN3 (CAN FD capable), 2 × FlexRay 2.1, 1 × ENET (10/100 MII/RMII, AVB, IEEE 1588), 4 × DSPI, 4 × I²C, 16 × LINFlexD |
| Analog Peripherals | Two ADCs: one 10-bit (68 ch), one 12-bit (31 ch); three analog comparators; Cross Trigger Unit for synchronized sampling |
| Security | HSMv2 with secure boot, cryptographic acceleration (AES-128/256, SHA-256, RSA), PASS life-cycle management, and tamper detection |
Pinout & Package
SPC5746BBK1AMKU2 is housed in a 176-pin LQFP-EP (exposed pad) package with 0.5 mm pitch, optimized for thermal dissipation and automotive board-level reliability. Pin assignment follows NXP's standardized MPC5746C family mapping, supporting configurable I/O domains for FlexCAN, LINFlexD, Ethernet, and general-purpose GPIO.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage IO supply rails | Independent 3.3 V or 5 V supplies for I/O banks; enable mixed-voltage interface design |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated input for e200z4/z2 cores; supports internal voltage regulation or external 1.25 V source |
| VDD_HV_FLA | Flash memory supply | 3.3 V supply for flash programming/erase; internally regulated when VDD_HV_A = 5 V; shorted to VDD_HV_A when 3.3 V |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal; critical for FMPLL reference and system clock stability |
| CAN0_TX / CAN0_RX | FlexCAN0 differential transceiver pins | Direct connection to CAN physical layer; supports CAN FD up to 5 Mbps with programmable bit timing |
| ETH_MDIO / ETH_MDC / ETH_RXD[0:3] / ETH_TXD[0:3] | Ethernet PHY interface | RMII/MII-compliant signals for 10/100 Ethernet; enables time-sensitive networking (TSN) via IEEE 1588 timestamping |
| JTAG_TCK / JTAG_TMS / JTAG_TDI / JTAG_TDO / JTAG_nTRST | Nexus Class 3+ debug interface | IEEE-ISTO 5001-2008 compliant; supports real-time trace, non-intrusive debugging, and safety-critical validation |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core deterministic execution | Independent e200z4 and e200z2 cores with dedicated interrupt controllers and shared memory coherency via crossbar-enables separation of safety-critical and non-safety tasks |
| End-to-end ECC protection | SECDED (single-error correction, double-error detection) applied to all bus transactions across flash, SRAM, and peripherals-ensures data integrity in harsh automotive environments |
| Hardware Security Module v2 (HSMv2) | On-die cryptographic engine supporting AES-128/256, SHA-256, RSA-2048, secure boot, key provisioning, and anti-tamper monitoring-meets UNECE R155/R156 requirements |
| ASIL-B certified subsystems | FCCU fault collection, SMPU memory protection, STCU self-test, and user MBIST-all validated per ISO 26262 Part 5 Annex D-reduces functional safety integration effort |
| Multi-protocol communication hub | Simultaneous operation of 8 CAN FD channels, dual FlexRay, Ethernet AVB, and LIN allows consolidation of body, powertrain, and ADAS networks into a single domain controller |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) Domain Controller |
|---|---|
Use Scenario: Real-time combustion timing, air-fuel ratio control, and knock detection in gasoline/diesel engines under wide ambient (-40°C to +125°C) and transient load conditions. IC Role / Device Role / Timing Role: Primary compute engine executing AUTOSAR-compliant MCAL drivers, managing sensor fusion (crank/cam, MAP, O2), and actuating fuel injectors and ignition coils with sub-microsecond jitter. Use Value: Dual-core deterministic scheduling ensures hard real-time deadlines for spark/fuel events while offloading CAN FD diagnostics and OTA update handling to the z2 core-no task preemption risk. |
Use Scenario: Sensor data aggregation and preprocessing from radar, camera, and ultrasonic modules in L2+ vehicle architectures requiring low-latency decision loops and secure firmware updates. IC Role / Device Role / Timing Role: Central domain controller running adaptive AUTOSAR OS, coordinating time-synchronized data exchange over CAN FD and Ethernet AVB with IEEE 1588 timestamping. Use Value: Integrated HSMv2 enables secure boot and encrypted OTA updates; 8 CAN FD channels support multi-radar cluster communication without external protocol bridges. |
| Electric Powertrain Inverter Control | Chassis Domain Controller |
Use Scenario: Closed-loop motor control for traction inverters using field-oriented control (FOC), with real-time current/voltage sensing and thermal monitoring in high-noise EV power systems. IC Role / Device Role / Timing Role: High-speed eMIOS timer subsystem drives PWM generation (up to 200 kHz), while ADC0/ADC1 sample phase currents and DC-link voltage with synchronized triggering. Use Value: 12-bit ADC with cross-trigger unit ensures <100 ns timing correlation between PWM edges and current sampling-critical for minimizing torque ripple and inverter losses. |
Use Scenario: Integration of brake-by-wire, steer-by-wire, and suspension control functions requiring coordinated actuation, redundancy management, and fail-operational behavior. IC Role / Device Role / Timing Role: Safety-managed dual-core platform executing ASIL-B software partitions, with SMPU-enforced memory isolation and FCCU-monitored fault injection for diagnostic coverage. Use Value: On-chip ECC, STCU, and user MBIST provide >90% diagnostic coverage for random hardware faults-reducing need for external safety monitors and simplifying ISO 26262 FMEDA. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5746CBK1AMJU2 | 256-pin MAPBGA package; identical core, memory, and peripheral configuration; higher pin count enables more CAN/FlexRay routing and enhanced thermal performance | Better suited for space-constrained ECU designs requiring higher I/O density and improved heat dissipation in under-hood environments | Select when PCB layout requires finer pitch, higher signal integrity for high-speed Ethernet, or greater thermal headroom at 150°C junction temperature |
| SPC574S24B1MLU2 | Single-core e200z4 (160 MHz); 2 MB flash; 256 KB SRAM; no FlexRay; 6 × FlexCAN; HSMv1 (not v2); ASIL-B certified but fewer safety mechanisms | Targeted at cost-sensitive powertrain ECUs where FlexRay and dual-core determinism are not required | Choose for entry-level engine management or transmission control where reduced feature set lowers BOM cost and software complexity |
Compared with SPC5746BBK1AMKU2, MPC5746CBK1AMJU2 offers superior thermal and routing scalability in BGA form factor, while SPC574S24B1MLU2 trades FlexRay, dual-core, and HSMv2 for lower cost and footprint-making it suitable only for non-FlexRay, single-domain applications.
Availability
SPC5746BBK1AMKU2 is available at Aetrix Electronics and suitable for engine control units, ADAS domain controllers, and electric powertrain inverters requiring stable component supply, long-term automotive lifecycle support, and ASIL-B-certified silicon.
Supply support for SPC5746BBK1AMKU2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in functional safety and automotive-grade microcontrollers.
The SPC5746BBK1AMKU2 belongs to NXP's SPC574x automotive MCU family, engineered specifically for next-generation domain controllers and safety-critical powertrain systems demanding ASIL-B compliance, multi-protocol connectivity, and hardware-accelerated security.
FAQ
What is the maximum operating temperature range for the SPC5746BBK1AMKU2?
The SPC5746BBK1AMKU2 is qualified for operation from –40°C to +125°C ambient temperature (Ta), with junction temperature (Tj) rated up to +150°C. This specification meets AEC-Q100 Grade 1 requirements and supports deployment in under-hood automotive environments including engine control units and transmission control modules where thermal stress is significant. The device incorporates thermal monitoring circuitry and supports dynamic thermal throttling via its System Timer Modules (STM).
Does the SPC5746BBK1AMKU2 support CAN FD, and how many channels are available?
Yes, the SPC5746BBK1AMKU2 supports CAN FD on all eight integrated FlexCAN3 modules (FlexCAN0 through FlexCAN7), each configurable for classical CAN or CAN FD operation up to 5 Mbps. The controller includes programmable bit timing, flexible data length (up to 64 bytes), and built-in CRC protection-enabling high-bandwidth communication for modern ECU architectures such as domain controllers and battery management systems.
How does the SPC5746BBK1AMKU2 implement functional safety per ISO 26262?
The SPC5746BBK1AMKU2 achieves ISO 26262 ASIL-B compliance through integrated hardware safety mechanisms including Fault Collection and Control Unit (FCCU), System Memory Protection Unit (SMPU) with 32 region descriptors, end-to-end ECC on all memory and buses, STCU for structural self-test, and user-accessible MBIST. These features are documented in NXP's FS Functional Safety Manual and certified by TÜV SÜD for use in safety-related automotive software components.
What package type and pin count does the SPC5746BBK1AMKU2 use?
The SPC5746BBK1AMKU2 uses a 176-pin LQFP-EP (Low-Profile Quad Flat Package with Exposed Pad) package with 0.5 mm pitch. The exposed thermal pad enhances heat dissipation in automotive applications, and the pinout is fully compatible with the MPC5746C family reference designs. This package supports standard reflow soldering processes and is optimized for mechanical robustness in vibration-prone environments.
Is the SPC5746BBK1AMKU2 pin-compatible with other members of the MPC5746C family?
No, the SPC5746BBK1AMKU2 is not pin-compatible with other MPC5746C variants such as the 256-pin MAPBGA (e.g., MPC5746CBK1AMJU2) or 324-pin MAPBGA packages. While all share identical electrical functionality and register-level compatibility, the 176-pin LQFP-EP footprint has unique pin assignments and I/O multiplexing. Board-level migration requires PCB redesign, though software and driver libraries remain fully reusable across the family.
SPC5746BBK1AMKU2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z4
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, Ethernet, FlexRay, I2C, LINbus, SPI
- Peripherals:
- DMA, I2S, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 3.15V ~ 5.5V
- Data Converters:
- A/D 36x10b, 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746BBK1AMKU2 FAQ
1.How can I place an order for SPC5746BBK1AMKU2 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746BBK1AMKU2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746BBK1AMKU2 reliable?
The price and inventory of SPC5746BBK1AMKU2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746BBK1AMKU2 is usually 5 days.
3.What payment methods are accepted for SPC5746BBK1AMKU2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746BBK1AMKU2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746BBK1AMKU2?
SPC5746BBK1AMKU2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746BBK1AMKU2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746BBK1AMKU2?
For technical support, including SPC5746BBK1AMKU2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746BBK1AMKU2 requirements.
6.How does Aetrix verify that SPC5746BBK1AMKU2 is sourced from the original manufacturer or authorized distributors?
All SPC5746BBK1AMKU2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746BBK1AMKU2 meets industry standards.
7.What is the process for return or replacement of SPC5746BBK1AMKU2?
All SPC5746BBK1AMKU2 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746BBK1AMKU2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746BBK1AMKU2 part is unused and in its original packaging.
Return procedure for SPC5746BBK1AMKU2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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