NXP Semiconductors SPC5746BSK1AMKU2
- Part No.:
- SPC5746BSK1AMKU2
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5746BSK1AMKU2.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5746BSK1AMKU2 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated FlexCAN FD, Ethernet AVB, and FlexRay controllers. It supports ISO 26262 ASIL-B functional safety and targets engine control units, transmission control modules, and chassis domain controllers.
For engineers reviewing the SPC5746BSK1AMKU2 datasheet, SPC5746BSK1AMKU2 pinout, SPC5746BSK1AMKU2 application, or SPC5746BSK1AMKU2 equivalent, key selection criteria include dual-core deterministic timing, 8 FlexCAN FD channels with message RAM, 10/100 Ethernet with IEEE 1588 timestamping, and 256-ball MAPBGA package compatibility for high-integration powertrain systems.
Technical Context
The SPC5746BSK1AMKU2 implements a tightly coupled dual-core architecture where the e200z4 core handles real-time safety-critical tasks (e.g., fuel injection timing) while the e200z2 manages communication stacks and diagnostics. Both cores share access to memory via a crossbar switch and are protected by a System Memory Protection Unit (SMPU) with 32 region descriptors.
Its clock system integrates FMPLL, multiple IRCs (FIRC/SIRC), and crystal oscillators (FXOSC/SXOSC), enabling precise timing control across domains. The device uses SECDED ECC across all bus masters and memory interfaces, covering 64-bit data and 29-bit addresses for fault detection and correction in automotive environments.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160 MHz e200z4 + 80 MHz e200z2, supporting VLE for code density and single-precision floating-point operations |
| Flash Memory | 3 MB on-chip flash with triple-port controller, EEE support, and RWW partitioning for concurrent read/write during runtime |
| SRAM | 384 KB distributed across three RAM ports with ECC protection and optional 512 KB configuration |
| FlexCAN FD | 8 channels with CAN FD protocol support, dedicated message RAM per channel, and time-triggered communication capability |
| Ethernet Interface | 10/100 ENET complex with AVB, IEEE 1588 hardware timestamping, MII/RMII, and multi-queue support |
| Functional Safety | ISO 26262 ASIL-B certified; includes HSMv2 security module, FCCU fault collector, and SMPU memory protection |
| Package | 256-ball MAPBGA (MJ package code), 17 × 17 mm, 0.8 mm pitch, RoHS-compliant, automotive-grade (-40°C to +125°C) |
Pinout & Package
SPC5746BSK1AMKU2 is housed in a 256-ball MAPBGA (package code MJ) with 0.8 mm ball pitch and thermal pad. Pin assignments follow NXP's standard MPC5746C pinout layout, supporting configurable I/O domains for FlexCAN, LINFlexD, Ethernet, and general-purpose signals.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage I/O supply rails | Independent 3.3 V or 5 V supplies for I/O banks; enable mixed-voltage interface design with isolated voltage domains |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated input for e200z4/z2 cores; requires external decoupling per NXP's Cfp_reg specification (1.32–3 µF) |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal for primary clock source; enables high-accuracy timing for engine control loops |
| SXOSC_IN / SXOSC_OUT | 32 kHz real-time clock oscillator | Connects to 32 kHz crystal for RTC and low-power wake-up; maintains timekeeping during stop modes |
| ETH_MDIO / ETH_MDC / ETH_RXD[0:3] / ETH_TXD[0:3] | Ethernet physical layer interface | Direct RMII/MII connection to PHY; MDIO/MDC enable auto-negotiation and register configuration without host intervention |
| CAN0_TX / CAN0_RX … CAN7_TX / CAN7_RX | FlexCAN FD transceiver I/O | Dedicated differential pairs per channel; each supports bit rates up to 5 Mbps and payload lengths up to 64 bytes |
Key Features
| Feature | Design Value |
|---|---|
| Dual-core deterministic execution | e200z4 and e200z2 cores operate independently with shared memory arbitration, enabling ASIL-B software partitioning and lockstep-free safety mechanisms |
| End-to-end ECC protection | SECDED coverage across all bus masters, flash, SRAM, and peripheral registers - detects double-bit errors and corrects single-bit errors in real time |
| Hardware Security Module v2 (HSMv2) | Integrated cryptographic accelerator supporting AES-128/256, SHA-256, RSA-2048, and secure boot with key provisioning and life-cycle management |
| Configurable I/O domains | Per-pin voltage domain assignment allows simultaneous 3.3 V and 5 V signaling on same package; eliminates level-shifter components in mixed-signal designs |
| FlexRay 2.1 dual-channel controller | Full protocol stack support including static/dynamic segments, synchronization, and fault-tolerant communication at up to 10 Mbps per channel |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance Systems (ADAS) Domain Controller |
|---|---|
Use Scenario: Real-time combustion timing, air-fuel ratio calculation, and knock detection in gasoline/diesel engines. IC Role / Device Role / Timing Role: Primary compute engine executing ASIL-B safety-critical control algorithms with deterministic latency under 10 µs interrupt response. Use Value: Dual-core separation enables independent calibration updates on e200z2 while e200z4 maintains closed-loop actuator control without interruption. |
Use Scenario: Sensor fusion hub aggregating radar, camera, and ultrasonic inputs for adaptive cruise control and automatic emergency braking. IC Role / Device Role / Timing Role: High-bandwidth communication orchestrator routing CAN FD, Ethernet AVB, and FlexRay traffic with hardware timestamping and priority queuing. Use Value: IEEE 1588 PTP hardware support ensures sub-microsecond time synchronization across distributed ADAS sensors for coherent event correlation. |
| Electric Powertrain Inverter Control | Chassis Domain Controller |
Use Scenario: Closed-loop motor phase current regulation, DC-link voltage monitoring, and IGBT gate drive sequencing in traction inverters. IC Role / Device Role / Timing Role: Real-time PWM generation via eMIOS with cross-triggered ADC sampling synchronized to switching events. Use Value: 64-channel eMIOS + CTU enables precise dead-time insertion, overcurrent protection, and predictive torque control at 20 kHz switching frequencies. |
Use Scenario: Centralized brake-by-wire, steering assist, and suspension damping coordination across vehicle subsystems. IC Role / Device Role / Timing Role: Safety gateway managing inter-domain communication between powertrain, body, and ADAS networks with firewall and message filtering. Use Value: Integrated FlexCAN FD (8 channels) and Ethernet AVB allow simultaneous high-priority actuator commands and diagnostic logging without bandwidth contention. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5746C SK1AMJU2 | Same silicon die, identical core configuration and peripheral set; differs only in qualification status (S = automotive qualified vs. SPC = sample part number prefix) | Identical use cases; SK1AMJU2 is production-grade variant with full AEC-Q100 Grade 1 qualification and extended lifecycle support | Select SK1AMJU2 for volume production; SPC5746BSK1AMKU2 is functionally identical but intended for early evaluation and design-in phases |
| SPC5777MK0MLU2 | Higher-performance derivative: 240 MHz e200z7 core, 4 MB flash, 512 KB SRAM, additional FlexCAN FD channels (12), and enhanced HSMv3 | Targets next-gen zonal architectures requiring higher compute throughput and larger secure firmware partitions | Choose SPC5777MK0MLU2 when >160 MHz deterministic performance, >3 MB flash, or HSMv3 crypto acceleration is required |
Compared with SPC5746BSK1AMKU2, MPC5746C SK1AMJU2 offers identical functionality with formal automotive qualification, while SPC5777MK0MLU2 delivers higher clock speed, memory capacity, and security features - making it suitable for future-proofing in evolving E/E architectures.
Availability
SPC5746BSK1AMKU2 is available at Aetrix Electronics and suitable for engine control units, chassis domain controllers, electric powertrain inverters, and ADAS domain controllers requiring stable component supply across long automotive product lifecycles.
Supply support for SPC5746BSK1AMKU2 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in Power Architecture® and functional safety certification.
The SPC5746BSK1AMKU2 belongs to NXP's SPC57 family of automotive MCUs, designed specifically for ASIL-B real-time control in powertrain and chassis systems, emphasizing deterministic timing, memory safety, and multi-protocol communication integration.
FAQ
What is the core architecture of the SPC5746BSK1AMKU2?
The SPC5746BSK1AMKU2 integrates two Power Architecture® cores: a 160 MHz e200z4 dual-issue CPU with 8 KB instruction cache and 4 KB data cache, and an 80 MHz e200z2 single-issue CPU. Both support Variable Length Encoding (VLE) and single-precision floating-point operations. The SPC5746BSK1AMKU2 uses a crossbar switch to enable concurrent access to peripherals and memory, ensuring deterministic real-time behavior for automotive control applications.
Does the SPC5746BSK1AMKU2 support CAN FD, and how many channels are available?
Yes, the SPC5746BSK1AMKU2 supports CAN FD across eight independent FlexCAN modules (FlexCAN0–FlexCAN7), each with dedicated message RAM and configurable bit rates up to 5 Mbps. Each channel supports payloads up to 64 bytes and includes hardware timestamping, loopback testing, and error counters - essential for high-bandwidth diagnostics and control messaging in modern vehicle networks.
What package type and pin count does the SPC5746BSK1AMKU2 use?
The SPC5746BSK1AMKU2 uses a 256-ball MAPBGA package (code MJ), measuring 17 mm × 17 mm with 0.8 mm ball pitch. This package supports automotive-grade thermal performance and mechanical reliability, and its pinout aligns with the MPC5746C family's standardized signal mapping - enabling drop-in compatibility with other members of the same footprint family.
Is the SPC5746BSK1AMKU2 qualified for automotive applications, and what safety standards does it meet?
Yes, the SPC5746BSK1AMKU2 is automotive-qualified per AEC-Q100 Grade 1 (−40°C to +125°C) and certified to ISO 26262 ASIL-B for functional safety. It includes hardware-level safety mechanisms such as end-to-end ECC, SMPU with 32 region descriptors, Fault Collection and Control Unit (FCCU), and Hardware Security Module v2 (HSMv2) - all validated for use in safety-critical powertrain and chassis control systems.
What development tools and software support are available for the SPC5746BSK1AMKU2?
NXP provides comprehensive support for the SPC5746BSK1AMKU2, including S32 Design Studio IDE, S32 Configuration Tool, AUTOSAR-compliant MCAL drivers, SafeRTOS and FreeRTOS BSPs, and reference examples for CAN FD, Ethernet AVB, and FlexRay. Debugging is enabled via JTAG/cJTAG and Nexus Class 3+ interfaces, with full visibility into both e200z4 and e200z2 cores during real-time execution.
SPC5746BSK1AMKU2 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z4
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, Ethernet, FlexRay, I2C, LINbus, SPI
- Peripherals:
- DMA, I2S, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 3.15V ~ 5.5V
- Data Converters:
- A/D 36x10b, 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746BSK1AMKU2 FAQ
1.How can I place an order for SPC5746BSK1AMKU2 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746BSK1AMKU2 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746BSK1AMKU2 reliable?
The price and inventory of SPC5746BSK1AMKU2 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746BSK1AMKU2 is usually 5 days.
3.What payment methods are accepted for SPC5746BSK1AMKU2?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746BSK1AMKU2 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746BSK1AMKU2?
SPC5746BSK1AMKU2 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746BSK1AMKU2 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746BSK1AMKU2?
For technical support, including SPC5746BSK1AMKU2 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746BSK1AMKU2 requirements.
6.How does Aetrix verify that SPC5746BSK1AMKU2 is sourced from the original manufacturer or authorized distributors?
All SPC5746BSK1AMKU2 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746BSK1AMKU2 meets industry standards.
7.What is the process for return or replacement of SPC5746BSK1AMKU2?
All SPC5746BSK1AMKU2 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746BSK1AMKU2, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746BSK1AMKU2 part is unused and in its original packaging.
Return procedure for SPC5746BSK1AMKU2:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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