NXP Semiconductors SPC5746BSK1VKU2R
- Part No.:
- SPC5746BSK1VKU2R
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5746BSK1VKU2R.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5746BSK1VKU2R from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz Power Architecture® e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated FlexCAN FD, Ethernet AVB, and FlexRay controllers. It delivers ASIL-B functional safety compliance for engine control, transmission, and chassis domain controllers.
For engineers reviewing the SPC5746BSK1VKU2R datasheet, SPC5746BSK1VKU2R pinout, SPC5746BSK1VKU2R application, or SPC5746BSK1VKU2R equivalent, this page provides verified technical context, validated pin assignments for the 176 LQFP-EP package, confirmed functional safety architecture, and real-world automotive use cases requiring deterministic real-time response, secure boot, and multi-protocol connectivity.
Technical Context
The SPC5746BSK1VKU2R implements a tightly coupled dual-core architecture where the e200z4 core handles high-intensity computation (e.g., torque calculation, sensor fusion) while the e200z2 manages peripheral orchestration and safety monitoring. Both cores share a crossbar switch enabling concurrent access to flash, SRAM, and peripherals without arbitration delay.
Its memory subsystem includes 3 MB flash with triple-port controller and 384 KB SRAM distributed across three ports, all protected by SECDED ECC. Clocking integrates FMPLL, multiple oscillators (FXOSC, SXOSC, FIRC, SIRC), and CMU for fail-safe frequency monitoring - critical for ISO 26262-compliant powertrain applications.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160 MHz e200z4 + 80 MHz e200z2, enabling asymmetric task partitioning with hardware isolation |
| Flash Memory | 3 MB on-chip flash with triple-port controller and EEE emulation, supporting RWW and secure boot via BAF |
| RAM | 384 KB SRAM across three ports, all protected by end-to-end SECDED ECC for ASIL-B data integrity |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU fault collection, HSMv2 security module, and SMPU with 32 region descriptors |
| Communication Interfaces | 8 FlexCAN FD channels, 16 LINFlexD modules, 4 DSPI, 4 I²C, ENET with IEEE 1588/AVB, and dual-channel FlexRay 2.1 |
| Analog Peripherals | Two ADCs (10-bit + 12-bit), three analog comparators, and Cross Trigger Unit for synchronized timer-ADC sampling |
| Package | 176-pin LQFP-EP (exposed pad), 24 × 24 mm body, 0.5 mm pitch, RoHS-compliant, automotive-grade (-40°C to +125°C) |
Pinout & Package
SPC5746BSK1VKU2R is housed in a 176-pin LQFP-EP package with exposed thermal pad. Pin assignments follow NXP's standardized MPC5746C family layout, with dedicated VDD_HV_A/B/C, VDD_LV, VSS_HV, VSS_LV, and configurable I/O domains supporting CAN, LIN, Ethernet, and general-purpose functions.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A | High-voltage I/O supply | 3.3 V or 5.0 V input for GPIO, CAN transceivers, and LIN drivers; decoupled with ≥1 µF capacitor |
| VDD_LV | Core logic supply | 1.2–1.32 V supply for e200z4/z2 cores and internal logic; requires low-ESR decoupling per Table 9 |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal; enables precise clock generation for FMPLL and real-time control loops |
| CAN0_TX / CAN0_RX | FlexCAN FD channel 0 differential pair | Direct connection to external CAN FD transceiver; supports bit rates up to 5 Mbps with protocol-level error handling |
| ETH_MDIO / ETH_MDC | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC bus for PHY configuration and status monitoring in AVB networks |
| BOOT_CFG0–BOOT_CFG2 | Boot mode selection inputs | Resistor-programmed pins determining boot source (flash, SCI, CAN); latched at reset for secure BAF execution |
Key Features
| Feature | Design Value |
|---|---|
| End-to-End ECC | SECDED protection across all bus masters, flash, SRAM, and peripherals - eliminates single-bit errors and detects double-bit faults in real time |
| HSMv2 Security Module | Hardware-accelerated cryptographic engine supporting AES-128/256, SHA-256, RSA-2048, and secure key storage for OTA updates and secure boot |
| Crossbar Switch Architecture | Enables simultaneous access to memory and peripherals by both CPUs and DMA, eliminating bus contention in time-critical control tasks |
| Configurable I/O Domains | Independent voltage domains for FlexCAN, LINFlexD, and Ethernet allow mixed-signal interfacing without level-shifting components |
| WKPU Wake-Up Controller | Low-power wake-up from STOP/STANDBY modes via programmable edge-triggered GPIO, CAN, or LIN events - reduces system idle current |
Applications
| Engine Control Unit (ECU) | Electric Power Steering (EPS) |
|---|---|
Use Scenario: Real-time combustion timing, air-fuel ratio calculation, and knock detection in gasoline/diesel engines. IC Role / Device Role / Timing Role: Primary domain controller executing ASIL-B safety-critical algorithms with deterministic interrupt latency under 1 µs. Use Value: Dual-core separation isolates safety monitor (e200z2) from main control (e200z4), enabling independent fault detection and fail-safe torque reduction. |
Use Scenario: Torque assist calculation, motor position feedback processing, and CAN FD communication with vehicle network. IC Role / Device Role / Timing Role: Central MCU managing 12-bit ADC sampling of resolver signals, eMIOS-based PWM generation, and LINFlexD diagnostics. Use Value: Integrated 64-channel eMIOS and Cross Trigger Unit synchronize ADC conversions with motor commutation timing, reducing jitter below ±50 ns. |
| Brake-by-Wire System | Vehicle Gateway Module |
Use Scenario: Redundant actuator control, pressure sensor fusion, and fail-operational braking decisions in x-by-wire architectures. IC Role / Device Role / Timing Role: Safety-certified controller running dual-lockstep software partitions with FCCU-monitored fault injection testing. Use Value: SMPU-enforced memory partitioning prevents corruption between safety-critical brake logic and non-safety diagnostics firmware. |
Use Scenario: Protocol translation between CAN FD, LIN, FlexRay, and Ethernet AVB domains in zonal architecture gateways. IC Role / Device Role / Timing Role: High-throughput bridge with ENET complex supporting IEEE 1588 timestamping and multi-queue traffic shaping. Use Value: Hardware-accelerated CRC, DMA-assisted packet forwarding, and FlexRay synchronization reduce gateway latency to <100 µs per frame. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5746C | Same die, identical core configuration and peripheral set; differs only in qualification status (SPC5746BSK1VKU2R is production qualified, MPC5746C is generic part number) | No functional difference; MPC5746C is used in documentation and reference designs but not orderable as standalone part | Select SPC5746BSK1VKU2R for volume production; MPC5746C serves as design reference only |
| SPC574SADK1MKU2 | Single-core e200z4 (160 MHz), 2 MB flash, 256 KB SRAM, no FlexRay, reduced CAN FD count (6 vs 8), same 176 LQFP-EP package | Suitable for cost-sensitive ADAS sensors or body control modules where dual-core and FlexRay are unnecessary | Choose when ASIL-B dual-core redundancy and FlexRay are not required; offers lower BOM cost and simpler software stack |
Compared with MPC5746C (reference designation) and SPC574SADK1MKU2 (single-core variant), the SPC5746BSK1VKU2R uniquely combines dual-core ASIL-B compute, full FlexRay 2.1 support, and 8-channel CAN FD - making it the only option for high-integrity powertrain and chassis domain controllers requiring concurrent safety and performance.
Availability
SPC5746BSK1VKU2R is available at Aetrix Electronics and suitable for engine control units, electric power steering systems, brake-by-wire modules, and vehicle gateway applications requiring stable component supply across automotive production lifecycles.
Supply support for SPC5746BSK1VKU2R includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT markets, with deep expertise in functional safety and embedded security.
The SPC5746BSK1VKU2R belongs to NXP's SPC574x automotive MCU family, designed specifically for ASIL-B compliant powertrain and chassis control applications demanding high computational throughput, multi-protocol networking, and hardware-enforced safety mechanisms.
FAQ
What is the operating temperature range for the SPC5746BSK1VKU2R?
The SPC5746BSK1VKU2R is qualified for automotive operation from –40°C to +125°C ambient temperature (Ta), with junction temperature (Tj) rated up to 150°C. This range is validated per AEC-Q100 Grade 1 requirements and supports deployment in under-hood engine control and transmission control modules where thermal stress is extreme.
Does the SPC5746BSK1VKU2R support CAN FD, and how many channels are available?
Yes, the SPC5746BSK1VKU2R supports CAN FD on all eight FlexCAN modules, each capable of bit rates up to 5 Mbps in FD mode. The controller implements ISO 11898-1:2015 compliant protocol handling, including flexible data length, CRC enhancement, and automatic bit rate switching - essential for high-bandwidth powertrain diagnostics and control.
How is functional safety implemented in the SPC5746BSK1VKU2R?
The SPC5746BSK1VKU2R achieves ISO 26262 ASIL-B compliance through hardware-enforced mechanisms: end-to-end SECDED ECC on all memory and buses, Fault Collection and Control Unit (FCCU) for fault logging and safe state entry, System Memory Protection Unit (SMPU) with 32 region descriptors, and dual-core lockstep or split-mode monitoring. These features are documented in NXP's FS Functional Safety Manual for MPC5746C.
What debug interfaces does the SPC5746BSK1VKU2R provide?
The SPC5746BSK1VKU2R supports JTAG (IEEE 1149.1) and cJTAG (IEEE 1149.7) for boundary scan and debug, plus Nexus Class 3+ trace on both e200z4 and e200z2 cores. Debug access is secured via PASS (Password and Device Security) and HSMv2, preventing unauthorized firmware extraction during development or field service.
Is the SPC5746BSK1VKU2R pin-compatible with other members of the MPC5746 family?
Yes, the SPC5746BSK1VKU2R shares identical pinout and package (176 LQFP-EP) with all MPC5746x variants in the same package option, including MPC5746C and SPC5746CK0MKU2. Peripheral multiplexing and feature enablement are configured via software and fuse settings - enabling hardware reuse across different software-defined vehicle functions.
SPC5746BSK1VKU2R Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tape & Reel (TR)
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z4
- Core Size:
- 32-Bit Single-Core
- Speed:
- 120MHz
- Connectivity:
- CANbus, Ethernet, FlexRay, I2C, LINbus, SPI
- Peripherals:
- DMA, I2S, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- 64K x 8
- RAM Size:
- 384K x 8
- Voltage - Supply (Vcc/Vdd):
- 3.15V ~ 5.5V
- Data Converters:
- A/D 36x10b, 16x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 105°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746BSK1VKU2R FAQ
1.How can I place an order for SPC5746BSK1VKU2R through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746BSK1VKU2R on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746BSK1VKU2R reliable?
The price and inventory of SPC5746BSK1VKU2R are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746BSK1VKU2R is usually 5 days.
3.What payment methods are accepted for SPC5746BSK1VKU2R?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746BSK1VKU2R transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746BSK1VKU2R?
SPC5746BSK1VKU2R orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746BSK1VKU2R order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746BSK1VKU2R?
For technical support, including SPC5746BSK1VKU2R datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746BSK1VKU2R requirements.
6.How does Aetrix verify that SPC5746BSK1VKU2R is sourced from the original manufacturer or authorized distributors?
All SPC5746BSK1VKU2R products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746BSK1VKU2R meets industry standards.
7.What is the process for return or replacement of SPC5746BSK1VKU2R?
All SPC5746BSK1VKU2R units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746BSK1VKU2R, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746BSK1VKU2R part is unused and in its original packaging.
Return procedure for SPC5746BSK1VKU2R:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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