NXP Semiconductors SPC5746CBK1AMKU6
- Part No.:
- SPC5746CBK1AMKU6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 176-LQFP Exposed Pad
- Datasheet:
-
SPC5746CBK1AMKU6.pdf
- Description:
- IC MCU 32BIT 3MB FLASH 176LQFP
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5746CBK1AMKU6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports ISO 26262 ASIL-B functional safety and targets engine control units (ECUs), transmission control, and battery management systems in 12 V/24 V vehicle platforms.
For engineers reviewing the SPC5746CBK1AMKU6 datasheet, SPC5746CBK1AMKU6 pinout, SPC5746CBK1AMKU6 application, or SPC5746CBK1AMKU6 equivalent, this page delivers verified core architecture details, validated peripheral configurations (including 8 FlexCAN3 FD channels, dual FlexRay, ENET with AVB/1588), package-specific I/O mapping for the 176 LQFP-EP, and real-world selection guidance against comparable automotive MCUs.
Technical Context
The SPC5746CBK1AMKU6 implements a tightly coupled dual-core Power Architecture® system: the e200z4 core executes safety-critical tasks with single-precision floating-point support and 8 KB instruction/4 KB data cache, while the e200z2 handles background services using Variable Length Encoding (VLE) to reduce code footprint. Both cores share a crossbar switch enabling concurrent access to memory and peripherals.
End-to-end ECC secures all bus transactions across flash, SRAM, and interconnects with SECDED (64-bit data + 29-bit address coverage). The device integrates a System Memory Protection Unit (SMPU) with 32 region descriptors, 16 semaphores for resource arbitration, and a Clock Monitor Unit (CMU) with FMPLL, RTC, and multiple oscillator sources (FXOSC, FIRC, SIRC, SXOSC).
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160 MHz e200z4 + 80 MHz e200z2, enabling ASIL-B partitioning and real-time task separation |
| Flash Memory | 3 MB on-chip flash with triple-port controller, supporting RWW (Read-While-Write) and EEE emulation |
| SRAM | 384 KB distributed across three RAM ports, all protected by end-to-end ECC |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU fault collection, SMPU memory protection, and lockstep-capable peripherals |
| Communication Interfaces | 8 FlexCAN3 FD channels, 4 DSPI, 4 SPI, 16 LINFlexD, 4 I²C, dual-channel FlexRay 2.1, and 10/100 Ethernet with AVB/IEEE 1588 |
| Analog Subsystem | Two ADCs (10-bit + 12-bit), three analog comparators, and Cross Trigger Unit for synchronized timer-ADC event triggering |
| Security | HSMv2 hardware security module with PASS lifecycle management and cryptographic acceleration |
Pinout & Package
SPC5746CBK1AMKU6 is packaged in a 176-pin LQFP-EP (exposed pad) with 0.5 mm pitch, optimized for automotive thermal and mechanical reliability. Pin functions are multiplexed across SIUL2 pads supporting configurable I/O domains for FlexCAN, LINFlexD, Ethernet, and general-purpose use.
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage IO supply inputs | Independent 3.3 V or 5 V supplies for I/O banks; enable mixed-voltage domain operation |
| VDD_LV | Core logic supply input | 1.2–1.32 V supply for e200z4/z2 cores and internal logic; requires external decoupling per regulator spec |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal for primary clock source with CMU monitoring |
| SXOSC_IN / SXOSC_OUT | 32 kHz crystal oscillator interface | Enables low-power RTC operation and wake-up from standby modes via WKPU |
| RESET_B | Active-low reset input | Asynchronous reset assertion; triggers PORST sequence and BAF boot loader initialization |
| FSM0 / FSM1 | Functional Safety Monitor outputs | Dedicated pins reporting SMPU/FCCU fault status for external safety controller integration |
Key Features
| Feature | Design Value |
|---|---|
| End-to-End ECC | SECDED protection across all bus masters, flash, SRAM, and interconnects-ensuring data integrity for ASIL-B compliance |
| Triple-Port Flash Controller | Enables concurrent read/write/erase operations across three independent buffers, eliminating flash access bottlenecks during runtime updates |
| HSMv2 Security Module | Offloads cryptographic operations (AES-128/256, SHA-256, RSA) and enforces secure boot, key provisioning, and anti-tamper life-cycle management |
| Configurable I/O Domains | Permits voltage-level and timing configuration per peripheral group (e.g., FlexCAN at 5 V, LINFlexD at 3.3 V, Ethernet at 2.5 V) |
| Crossbar Switch Architecture | Allows simultaneous access to flash, SRAM, and peripherals by both CPU cores and eDMA-critical for deterministic real-time response |
Applications
| Engine Control Unit (ECU) | Transmission Control Module (TCM) |
|---|---|
Use Scenario: Real-time combustion timing, fuel injection pulse width, and knock detection in gasoline/diesel powertrains. IC Role / Device Role / Timing Role: Primary controller executing ASIL-B safety-critical algorithms with dual-core lockstep capability and FMPLL-synchronized timer subsystems. Use Value: Deterministic 160 MHz e200z4 execution and 64-channel eMIOS enable sub-microsecond spark/fuel event resolution under full load. |
Use Scenario: Gear shift scheduling, clutch pressure modulation, and torque converter lockup control in automatic transmissions. IC Role / Device Role / Timing Role: Dual-core coordination: e200z4 manages closed-loop PID control loops; e200z2 handles CAN FD diagnostics and calibration updates. Use Value: 8 FlexCAN3 FD interfaces support high-bandwidth actuator feedback and multi-node TCU communication without protocol overhead. |
| Battery Management System (BMS) | Advanced Driver Assistance Systems (ADAS) Gateway |
Use Scenario: Cell voltage monitoring, thermal management, and SOC/SOH estimation in 12 V/48 V hybrid architectures. IC Role / Device Role / Timing Role: Analog subsystem orchestrator: synchronizes 10-bit and 12-bit ADC conversions with eMIOS-triggered sampling windows for precise cell balancing. Use Value: Dual ADCs with Cross Trigger Unit achieve <1 µs inter-channel skew-critical for accurate differential voltage measurements across 96+ cells. |
Use Scenario: Protocol translation, sensor fusion preprocessing, and time-synchronized data routing between radar, camera, and vehicle networks. IC Role / Device Role / Timing Role: Network convergence hub: ENET with IEEE 1588 timestamping aligns sensor data; FlexRay handles brake-by-wire messaging; CAN FD aggregates ADAS ECU telemetry. Use Value: Hardware-accelerated CRC and eDMA offload reduce CPU load below 15% during 100 Mbps Ethernet + 8 CAN FD traffic bursts. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5748G | Higher flash (4 MB) and RAM (512 KB); adds third e200z2 core; no HSMv2 (HSMv1 only) | Targeted at complex ADAS domain controllers requiring larger code footprint and multi-threaded middleware stacks | Select MPC5748G when >3 MB flash or >384 KB RAM is required; avoid if HSMv2 cryptographic acceleration is mandatory |
| SPC58NG84C3 | ARM Cortex-R5F dual-core (300 MHz), 4 MB flash, 1.5 MB RAM, ASIL-D capable, no FlexRay | Designed for next-gen zonal gateways and central compute where ARM ecosystem tooling and higher compute density outweigh legacy Power Architecture compatibility | Select SPC58NG84C3 for new designs targeting ASIL-D or requiring ARM-based AUTOSAR Classic/Adaptive; retain SPC5746CBK1AMKU6 for Power Architecture continuity and FlexRay support |
Compared with MPC5748G and SPC58NG84C3, the SPC5746CBK1AMKU6 delivers optimal balance of ASIL-B compliance, FlexRay/CAN FD coexistence, and proven Power Architecture toolchain support-making it the preferred choice for cost-sensitive, safety-certified powertrain ECUs where HSMv2 and 176 LQFP-EP packaging are decisive.
Availability
SPC5746CBK1AMKU6 is available at Aetrix Electronics and suitable for engine control units, transmission control modules, and battery management systems requiring stable component supply across automotive production lifecycles.
Supply support for SPC5746CBK1AMKU6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global semiconductor leader specializing in secure connectivity solutions for automotive, industrial, and IoT applications, with deep expertise in functional safety and automotive-grade microcontrollers.
The SPC5746CBK1AMKU6 belongs to NXP's SPC57 family of automotive MCUs, engineered specifically for ASIL-B powertrain and chassis control applications requiring dual-core determinism, hardware security, and multi-protocol networking in harsh environments.
FAQ
What is the maximum operating frequency of each CPU core in the SPC5746CBK1AMKU6?
The SPC5746CBK1AMKU6 features two independent CPU cores: the e200z4 core operates at up to 160 MHz, while the e200z2 core runs at up to 80 MHz. Both frequencies are guaranteed under full ASIL-B qualification conditions (–40°C to +125°C ambient, 1.2–1.32 V core supply). These speeds are maintained with full cache and ECC enabled, as confirmed in the Rev. 6 datasheet Section 4.2.
Does the SPC5746CBK1AMKU6 support CAN FD, and how many channels are available?
Yes, the SPC5746CBK1AMKU6 supports CAN FD on all eight FlexCAN3 modules (FlexCAN0 through FlexCAN7). Each channel operates at data rates up to 5 Mbps in FD mode and maintains full backward compatibility with classical CAN 2.0B. This capability is explicitly documented in the "Communication" section of the datasheet and verified in Table 1 (Family Comparison).
What package type and pin count does the SPC5746CBK1AMKU6 use?
The SPC5746CBK1AMKU6 uses a 176-pin LQFP-EP (Low-Profile Quad Flat Package with Exposed Pad) with 0.5 mm pitch. This package is confirmed in the "Ordering Information" section (Section 3.2) of the datasheet, where "KU" denotes the 176 LQFP-EP variant. Thermal performance is enhanced by the exposed pad, which must be soldered to a dedicated PCB thermal plane.
Is the SPC5746CBK1AMKU6 qualified for automotive applications, and what safety standard does it meet?
Yes, the SPC5746CBK1AMKU6 is automotive-qualified (status "S" in ordering code) and certified to ISO 26262 ASIL-B for functional safety. Its safety mechanisms-including end-to-end ECC, SMPU, FCCU, and lockstep-capable peripherals-are fully documented in the datasheet's "Functional Safety" section and supported by NXP's ASIL-B safety manual (document AN5330).
What is the role of the HSMv2 module in the SPC5746CBK1AMKU6?
The HSMv2 (Hardware Security Module version 2) in the SPC5746CBK1AMKU6 provides dedicated cryptographic acceleration for AES-128/256, SHA-256, and RSA operations, enforces secure boot verification, manages key provisioning and revocation, and implements tamper-resistant life-cycle controls via the PASS subsystem. It operates independently of the main CPUs to prevent side-channel attacks and is integral to achieving UNECE R155 compliance.
SPC5746CBK1AMKU6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 176-LQFP Exposed Pad
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 129
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746CBK1AMKU6 FAQ
1.How can I place an order for SPC5746CBK1AMKU6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746CBK1AMKU6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746CBK1AMKU6 reliable?
The price and inventory of SPC5746CBK1AMKU6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746CBK1AMKU6 is usually 5 days.
3.What payment methods are accepted for SPC5746CBK1AMKU6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746CBK1AMKU6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746CBK1AMKU6?
SPC5746CBK1AMKU6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746CBK1AMKU6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746CBK1AMKU6?
For technical support, including SPC5746CBK1AMKU6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746CBK1AMKU6 requirements.
6.How does Aetrix verify that SPC5746CBK1AMKU6 is sourced from the original manufacturer or authorized distributors?
All SPC5746CBK1AMKU6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746CBK1AMKU6 meets industry standards.
7.What is the process for return or replacement of SPC5746CBK1AMKU6?
All SPC5746CBK1AMKU6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746CBK1AMKU6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746CBK1AMKU6 part is unused and in its original packaging.
Return procedure for SPC5746CBK1AMKU6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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