NXP Semiconductors SPC5746CBK1AMMJ6
- Part No.:
- SPC5746CBK1AMMJ6
- Manufacturer:
- NXP Semiconductors
- Category:
- Microcontrollers
- Package:
- 256-LBGA
- Datasheet:
-
SPC5746CBK1AMMJ6.pdf
- Description:
- IC MCU 32BIT 3MB FLSH 256MAPPBGA
- Quantity:
- Payment:

- Shipping:

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Product details
Overview
SPC5746CBK1AMMJ6 from NXP Semiconductors is a dual-core automotive microcontroller featuring a 160 MHz e200z4 CPU and an 80 MHz e200z2 CPU, 3 MB on-chip flash, 384 KB SRAM with end-to-end ECC, and integrated HSMv2 security module. It supports CAN FD (8 FlexCAN channels), Ethernet AVB/1588, FlexRay, and ISO 26262 ASIL-B functional safety - deployed in engine control units and advanced driver assistance systems.
For engineers reviewing the SPC5746CBK1AMMJ6 datasheet, SPC5746CBK1AMMJ6 pinout, SPC5746CBK1AMMJ6 application, or SPC5746CBK1AMMJ6 equivalent, this page delivers verified core architecture, memory mapping, peripheral timing constraints, safety certification scope, and package-specific I/O allocation for production-grade automotive ECU design.
Technical Context
The SPC5746CBK1AMMJ6 implements a tightly coupled dual-core Power Architecture® system with crossbar-switch interconnect enabling concurrent access to flash, SRAM, and peripherals by both e200z4 and e200z2 cores. Its memory subsystem includes triple-port flash controller with three page buffers and SMPU-enforced memory protection across 32 regions at 16-byte granularity.
Real-time operation is supported by 64-channel eMIOS, 16 PITs, two STM modules, and hardware synchronization via Cross Trigger Unit between ADC conversions and timer events. Clock management integrates FMPLL, multiple IRC sources (FIRC/SIRC), FXOSC/SXOSC, and CMU-based monitoring for fail-safe timing integrity.
Key Specifications
| Parameter | Value and Actual Design Meaning |
|---|---|
| CPU Cores | Dual-core: 160 MHz e200z4 + 80 MHz e200z2, both with VLE encoding and single-precision FPU on z4 |
| Flash Memory | 3 MB on-chip flash with ECC, triple-port controller, and Boot Assist Flash (BAF) for serial programming |
| RAM | 384 KB on-chip SRAM across three ports, all protected by end-to-end SECDED ECC |
| Functional Safety | ISO 26262 ASIL-B certified; includes FCCU fault collection, PASS lifecycle management, and HSMv2 cryptographic acceleration |
| Communication Interfaces | 8 FlexCAN3 channels with CAN FD support, 4 DSPI, 4 SPI, 16 LINFlexD, 4 I²C, ENET (10/100 MII/RMII with AVB/1588), dual FlexRay |
| Analog Peripherals | Two ADCs: one 10-bit (68 ch), one 12-bit (31 ch); three analog comparators; Cross Trigger Unit for synchronized sampling |
| Package & Pin Count | 256-pin MAPBGA (MJ package code), 178 GPIOs, 246 total I/O pins including dedicated FlexCAN/LIN/Ethernet domains |
Pinout & Package
SPC5746CBK1AMMJ6 is housed in a 256-ball MAPBGA (package code MJ) with 0.8 mm pitch, thermally enhanced EPAD, and RoHS-compliant finish. The package supports automotive AEC-Q100 Grade 1 qualification (–40°C to +125°C).
| Pin/Terminal | Circuit Role | Design Meaning |
|---|---|---|
| VDD_HV_A / VDD_HV_B / VDD_HV_C | High-voltage I/O supply rails | Independent 3.3 V or 5 V supplies for I/O banks; enable mixed-voltage domain interfacing |
| VDD_LV | Core logic supply | 1.2–1.32 V regulated input for e200z4/z2 cores and internal logic; requires external decoupling per Table 9 |
| FXOSC_IN / FXOSC_OUT | Main crystal oscillator interface | Supports 8–40 MHz external crystal; feeds FMPLL for high-accuracy system clock generation |
| SXOSC_IN / SXOSC_OUT | 32 kHz real-time clock crystal | Drives RTC/API and low-power wake-up timing; enables precise timekeeping during stop modes |
| FMPLL_REFCLK | FMPLL reference clock input | Accepts external clock source (e.g., from FXOSC or FIRC) to configure PLL output frequencies up to 160 MHz |
| CAN0_TX / CAN0_RX | FlexCAN0 differential transceiver signals | Direct connection to external CAN transceiver; supports CAN FD data rates up to 5 Mbps |
| ENET_MDIO / ENET_MDC | Ethernet management interface | IEEE 802.3-compliant MDIO/MDC bus for PHY configuration and status monitoring |
| JTAG_TCK / JTAG_TMS / JTAG_TDI / JTAG_TDO | Nexus Class 3+ debug interface | IEEE-ISTO 5001-2008 compliant; enables full-core debugging, trace, and secure firmware loading |
Key Features
| Feature | Design Value |
|---|---|
| End-to-End ECC Protection | SECDED applied to all bus transactions (64-bit data + 29-bit address), covering flash, SRAM, and peripheral registers |
| Dual-Core Real-Time Determinism | e200z4 handles safety-critical tasks (ASIL-B), while e200z2 manages communication stacks and diagnostics - isolated via SMPU |
| HSMv2 Hardware Security Module | Accelerates AES-128/256, SHA-256, RSA-2048, and ECDSA; supports secure boot, key provisioning, and runtime attestation |
| Automotive Ethernet AVB Stack Support | Integrated ENET complex with multi-queue DMA, IEEE 1588 timestamping, and AVB traffic shaping for time-sensitive networking |
| Low-Power Wake-Up Capability | WKPU controller enables selective wake-up from STOP mode via LIN, CAN, FlexRay, or GPIO events without full core restart |
Applications
| Engine Control Unit (ECU) | Advanced Driver Assistance System (ADAS) Sensor Hub |
|---|---|
Use Scenario: Real-time combustion timing, fuel injection, and exhaust gas recirculation control in gasoline/diesel powertrains. IC Role / Device Role / Timing Role: Primary ASIL-B controller executing closed-loop PID algorithms with deterministic 100 µs interrupt latency and dual-core lockstep verification. Use Value: 3 MB flash stores calibrated maps and diagnostic routines; 8 FlexCAN FD channels handle high-bandwidth sensor fusion and actuator coordination. |
Use Scenario: Aggregating radar, camera, and ultrasonic inputs for object detection and path planning in L2+ ADAS platforms. IC Role / Device Role / Timing Role: Central processing node managing time-synchronized data ingestion via Ethernet AVB and CAN FD, with hardware timestamping for sensor fusion alignment. Use Value: Dual-core architecture isolates safety-critical perception stack (z4) from middleware (z2); ENET + FlexRay enable deterministic inter-ECU communication. |
| Electric Vehicle Battery Management System (BMS) | Vehicle Gateway / Domain Controller |
Use Scenario: Monitoring cell voltages, temperatures, and SOC/SOH estimation across 100+ battery cells in traction packs. IC Role / Device Role / Timing Role: High-precision analog front-end controller interfacing with 12-bit ADC and analog comparators for overvoltage/undervoltage fault detection. Use Value: End-to-end ECC ensures integrity of stored calibration data; HSMv2 secures firmware updates and cryptographic key storage for OTA compliance. |
Use Scenario: Bridging CAN FD, LIN, FlexRay, and Ethernet domains in zonal architectures to route messages between ADAS, infotainment, and chassis ECUs. IC Role / Device Role / Timing Role: Secure gateway processor enforcing firewall policies, message filtering, and protocol translation with hardware-accelerated crypto. Use Value: 16 LINFlexD modules manage body electronics; 4 I²C interfaces connect to PMICs and sensors; SMPU enforces strict memory isolation between domains. |
Equivalent & Alternatives
The following parts are listed as comparable options for similar dual-core automotive microcontroller applications.
| Alternative Part | Technical Difference | Application Difference | Selection Advice |
|---|---|---|---|
| MPC5748G | Higher RAM (512 KB), additional 12-bit ADC channel, no HSMv2; same dual-core e200z4/z2 and 3 MB flash | Lacks hardware security for secure boot and key management; suitable for non-security-critical gateways | Select when cryptographic acceleration and ASIL-B-certified security are not required, but higher RAM density is needed. |
| SPC58NG84C3 | ARM Cortex-R5F dual-core (300 MHz), 4 MB flash, 1.5 MB RAM, ISO 26262 ASIL-D ready, no Power Architecture | Architecturally incompatible; requires full software rework; targets next-gen ASIL-D systems | Choose only for new designs requiring ASIL-D certification and ARM ecosystem toolchain compatibility. |
Compared with MPC5746C-based alternatives, SPC5746CBK1AMMJ6 uniquely combines Power Architecture deterministic execution, mature AUTOSAR support, HSMv2, and ASIL-B certification in a production-proven 256 MAPBGA footprint - making it optimal for cost-sensitive, safety-aware automotive ECU upgrades.
Availability
SPC5746CBK1AMMJ6 is available at Aetrix Electronics and suitable for engine control units, ADAS sensor hubs, EV battery management systems, and vehicle gateways requiring stable component supply across extended automotive lifecycles.
Supply support for SPC5746CBK1AMMJ6 includes scheduled delivery planning, volume procurement assistance, BOM continuity management, traceable sourcing, and lifecycle availability coordination for OEM customers, industrial embedded developers, connected-device designers, and electronics production programs.
Manufacturer
NXP Semiconductors is a global leader in automotive semiconductors, delivering secure, reliable, and scalable solutions for electrification, ADAS, and digital transformation of vehicles.
The SPC5746CBK1AMMJ6 belongs to NXP's SPC57 family of Power Architecture® microcontrollers designed specifically for ASIL-B automotive powertrain and chassis control applications with integrated functional safety and security.
FAQ
What is the maximum operating frequency of the SPC5746CBK1AMMJ6's primary CPU core?
The SPC5746CBK1AMMJ6 features a 160 MHz e200z4 CPU core as its primary processing unit. This core supports single-precision floating-point operations, 8 KB instruction cache, and 4 KB data cache. The secondary e200z2 core operates at 80 MHz. Both cores use Variable Length Encoding (VLE) to reduce code size. Frequency is sustained under AEC-Q100 Grade 1 conditions (–40°C to +125°C ambient).
Does the SPC5746CBK1AMMJ6 support CAN FD, and how many channels are available?
Yes, the SPC5746CBK1AMMJ6 supports CAN FD across all eight FlexCAN3 modules (FlexCAN0 through FlexCAN7). Each channel is independently configurable for classic CAN or CAN FD operation with bit rates up to 5 Mbps in FD mode. CAN FD frames are processed with hardware CRC and error handling, and the eDMA controller offloads payload transfers to minimize CPU overhead.
What safety certifications apply to the SPC5746CBK1AMMJ6?
The SPC5746CBK1AMMJ6 is certified to ISO 26262 ASIL-B for specific safety mechanisms including ECC memory protection, FCCU fault reporting, watchdog timers (SWT/STM), and hardware memory protection (SMPU). It is not ASIL-D certified. Certification documentation covers failure modes, diagnostic coverage, and safe state behavior - validated per NXP's safety manual and FMEDA report for this exact part number.
How much on-chip flash and RAM does the SPC5746CBK1AMMJ6 include?
The SPC5746CBK1AMMJ6 integrates 3 MB of on-chip flash memory with ECC protection and triple-port architecture, plus 384 KB of on-chip SRAM distributed across three independent ports - all protected by end-to-end SECDED ECC. Flash supports RWW (Read-While-Write) partitions, and SRAM includes retention capability in low-power standby modes.
What package type and pin count does the SPC5746CBK1AMMJ6 use?
The SPC5746CBK1AMMJ6 uses a 256-ball MAPBGA package (package code MJ) with 0.8 mm ball pitch and thermally enhanced EPAD. It provides 178 general-purpose I/O pins and supports 246 total signal connections including dedicated domains for FlexCAN, LINFlexD, Ethernet, and analog functions. This package is qualified to AEC-Q100 Grade 1.
SPC5746CBK1AMMJ6 Specifications
- Product attributes
- Attribute value
- Manufacturer:
- NXP Semiconductors
- Package/Case:
- 256-LBGA
- Series:
- MPC57xx
- Packaging:
- Tray
- Product Status:
- Active
- Programmable:
- Not Verified
- Core Processor:
- e200z2, e200z4
- Core Size:
- 32-Bit Dual-Core
- Speed:
- 80MHz/160MHz
- Connectivity:
- CANbus, Ethernet, I2C, LINbus, SAI, SPI, USB, USB OTG
- Peripherals:
- DMA, LVD, POR, WDT
- Number of I/O:
- 178
- Program Memory Size:
- 3MB (3M x 8)
- Program Memory Type:
- FLASH
- EEPROM Size:
- -
- RAM Size:
- 512K x 8
- Voltage - Supply (Vcc/Vdd):
- 3V ~ 5.5V
- Data Converters:
- A/D 80x10b, 64x12b
- Oscillator Type:
- Internal
- Operating Temperature:
- -40°C ~ 125°C (TA)
- Grade:
- -
- Qualification:
- -
- Mounting Type:
- Surface Mount
- Supplier Device Package:
SPC5746CBK1AMMJ6 FAQ
1.How can I place an order for SPC5746CBK1AMMJ6 through Aetrix?
Please submit a Request for Quotation (RFQ) for SPC5746CBK1AMMJ6 on Aetrix. Our sales agent will provide a competitive quotation and guide you through the order confirmation once you accept the terms.
2.Are the price and stock information for SPC5746CBK1AMMJ6 reliable?
The price and inventory of SPC5746CBK1AMMJ6 are updated periodically and may fluctuate due to market conditions. Stock and pricing data are typically refreshed every 24 hours. Quotation validity for SPC5746CBK1AMMJ6 is usually 5 days.
3.What payment methods are accepted for SPC5746CBK1AMMJ6?
We accept Wire Transfer, PayPal, Credit Card, Western Union, MoneyGram, and Escrow for SPC5746CBK1AMMJ6 transactions.
Note: Certain payment methods may incur a processing fee.
4.How is shipping managed for SPC5746CBK1AMMJ6?
SPC5746CBK1AMMJ6 orders can be shipped via leading logistics carriers, including DHL, UPS, FedEx, TNT, or Registered Mail.
Once your SPC5746CBK1AMMJ6 order is processed, you will receive an email with the shipment details and tracking number.
Note: Tracking information may take up to 24 hours to appear. Express delivery typically takes 3–5 business days.
5.How can I obtain technical support or documentation for SPC5746CBK1AMMJ6?
For technical support, including SPC5746CBK1AMMJ6 datasheets, pinout diagrams, or application guidance, please contact our engineering support team. They can provide detailed documentation and assistance for your SPC5746CBK1AMMJ6 requirements.
6.How does Aetrix verify that SPC5746CBK1AMMJ6 is sourced from the original manufacturer or authorized distributors?
All SPC5746CBK1AMMJ6 products on Aetrix are procured from qualified distributors and authorized channels. Our dedicated quality assurance team conducts strict verification, including traceability checks and, if necessary, third-party testing. This ensures that SPC5746CBK1AMMJ6 meets industry standards.
7.What is the process for return or replacement of SPC5746CBK1AMMJ6?
All SPC5746CBK1AMMJ6 units undergo pre-shipment inspection (PSI). If there is an issue with SPC5746CBK1AMMJ6, returns or replacements are accepted under the following conditions:
1.Quantity discrepancies, incorrect items, or visible external defects (such as breakage or corrosion), acknowledged by Aetrix.
2.The issue is reported within 90 days of delivery.
3.The SPC5746CBK1AMMJ6 part is unused and in its original packaging.
Return procedure for SPC5746CBK1AMMJ6:
1.Submit a request within 90 days.
2.Obtain a Return Material Authorization (RMA) from Aetrix.
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